LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 136

IC MCU 32BIT 32KB FLASH 33HVQFN

LPC1343FHN33,551

Manufacturer Part Number
LPC1343FHN33,551
Description
IC MCU 32BIT 32KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Datasheets

Specifications of LPC1343FHN33,551

Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4944
935289655551

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC1343FHN33,551
Manufacturer:
NXP
Quantity:
780
NXP Semiconductors
UM10375
User manual
9.10.3.5.1 Data transfer
9.10.3.5 USB Control register (USBCtrl - 0x4002 0028)
Table 165. USB Transmit Packet Length register (USBTxPLen - address 0x4002 0024) bit
This register controls the data transfer operation of the USB device. It selects the endpoint
buffer that is accessed by the USBRxData and USBTxData registers and enables reading
and writing them. USBCtrl is a read/write register.
Table 166. USB Control register (USBCtrl - address 0x4002 0028) bit description
When the software wants to read the data from an endpoint buffer it should make the
Read Enable bit high and should program the logical endpoint number. The control logic
will first fetch the packet length to the receive packet length register. Also the hardware
fills the receive data register with the first word of the packet.
The software can now start reading the receive data register. When the end of packet is
reached the Read Enable bit will be disabled by the control logic and RxENDPKT bit is set
in the Device interrupt status register.
Bit
9:0
31:10 -
Bit
0
1
5:2
31:6 -
Symbol
RD_EN
WR_EN
LOG_ENDPOINT -
Symbol
PKT_LNGTH -
description
All information provided in this document is subject to legal disclaimers.
Value Description
-
Value
0
1
0
1
-
Rev. 2 — 7 July 2010
The remaining number of bytes to be written to the
selected endpoint buffer. This field is decremented by 4 by
hardware after each write to USBTxData. When this field
decrements to 0, the TxENDPKT bit will be set in
USBDevIntSt.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
Read mode control. Enables reading data from the OUT
endpoint buffer for the endpoint specified in the
LOG_ENDPOINT field using the USBRxData register.
This bit is cleared by hardware when the last word of
the current packet is read from USBRxData.
Read mode is disabled.
Read mode is enabled.
Write mode control. Enables writing data to the IN
endpoint buffer for the endpoint specified in the
LOG_ENDPOINT field using the USBTxData register.
This bit is cleared by hardware when the number of
bytes in USBTxLen have been sent.
Write mode is disabled.
Write mode is enabled.
Logical Endpoint number.
reserved bits. The value read from a reserved bit is not
defined.
Reserved, user software should not write ones to
Chapter 9: LPC13xx USB device controller
UM10375
© NXP B.V. 2010. All rights reserved.
138 of 333
Reset
value
0x000
NA
Reset
value
0
0
0x0
NA

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