LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 238
LPC1343FHN33,551
Manufacturer Part Number
LPC1343FHN33,551
Description
IC MCU 32BIT 32KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FHN33,551
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4944
935289655551
935289655551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FHN33,551
Manufacturer:
NXP
Quantity:
780
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NXP Semiconductors
UM10375
User manual
13.7.5 SSP0 Clock Prescale Register (SSP0CPSR - 0x4004 0010)
13.7.6 SSP0 Interrupt Mask Set/Clear Register (SSP0IMSC - 0x4004 0014)
Table 238: SSP0 Status Register (SSP0SR - address 0x4004 000C bit description
This register controls the factor by which the Prescaler divides the SSP peripheral clock
SSP_PCLK to yield the prescaler clock that is, in turn, divided by the SCR factor in
SSP0CR0, to determine the bit clock.
Table 239: SSP0 Clock Prescale Register (SSP0CPSR - address 0x4004 0010) bit description
Important: the SSP0CPSR value must be properly initialized or the SSP controller will not
be able to transmit data correctly.
In Slave mode, the SSP clock rate provided by the master must not exceed 1/12 of the
SSP peripheral clock selected in
relevant.
In master mode, CPSDVSR
This register controls whether each of the four possible interrupt conditions in the SSP
controller are enabled. Note that ARM uses the word “masked” in the opposite sense from
classic computer terminology, in which “masked” meant “disabled”. ARM uses the word
“masked” to mean “enabled”. To avoid confusion we will not use the word “masked”.
Bit
0
1
2
3
4
31:5
Bit
7:0
31:8
Symbol
TFE
TNF
RNE
RFF
BSY
-
Symbol
CPSDVSR This even value between 2 and 254, by which SSP_PCLK is
-
All information provided in this document is subject to legal disclaimers.
Description
Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is
empty, 0 if not.
Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1
Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is
empty, 1 if not.
Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if
not.
Busy. This bit is 0 if the SSP0 controller is idle, or 1 if it is
currently sending/receiving a frame and/or the Tx FIFO is not
empty.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
divided to yield the prescaler output clock. Bit 0 always reads
as 0.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 2 — 7 July 2010
min
= 2 or larger (even numbers only).
Table
24. The content of the SSP0CPSR register is not
Chapter 13: LPC13xx SSP
UM10375
© NXP B.V. 2010. All rights reserved.
Reset value
0
NA
Reset value
1
0
0
0
NA
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