LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 41

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
3.6 Reset
3.7 Brown-out detection
3.8 Power management
UM10375
User manual
3.8.1 Active mode
Reset has four sources on the LPC13xx: the RESET pin, Watchdog Reset, Power-On
Reset (POR), and Brown Out Detect (BOD). In addition, there is a software reset.
The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once
the operating voltage attains a usable level, starts the IRC causing reset to remain
asserted until the external Reset is de-asserted, the oscillator is running, and the flash
controller has completed its initialization.
On the assertion of a reset source external to the Cortex-M3 CPU (POR, BOD reset,
External reset, and Watchdog reset), following processes are initiated:
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
The LPC13xx includes four levels for monitoring the voltage on the V
falls below one of the four selected levels, the BOD asserts an interrupt signal to the
NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC
in order to cause a CPU interrupt; if not, software can monitor the signal by reading a
dedicated status register. An additional threshold level can be selected to cause a forced
reset of the chip.
The LPC13xx support a variety of power control features. In Active mode, when the chip is
running, power and clocks to selected peripherals can be optimized for power
consumption. In addition, there are three special modes of processor power reduction:
Sleep mode, Deep-sleep mode, and Deep power-down mode.
Remark: The Debug mode is not supported in Sleep, Deep-sleep, or Deep power-down
modes.
In Active mode, the ARM Cortex-M0 core and memories are clocked by the system clock,
and peripherals are clocked by the system clock or a dedicated peripheral clock.
The chip is in Active mode after reset and the default power configuration is determined
by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers. The power
configuration can be changed during run time.
1. The IRC starts up. After the IRC-start-up time (maximum of 6 μs on power-up), the
2. The boot code in the ROM starts. The boot code performs the boot tasks and may
3. The flash is powered up. This takes approximately 100 μs. Then the flash initialization
IRC provides a stable clock output.
jump to the flash.
sequence is started, which takes about 250 cycles.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Chapter 3: LPC13xx System configuration
DD
UM10375
© NXP B.V. 2010. All rights reserved.
pin. If this voltage
42 of 333