LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 135

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
9.10.3.3 USB Receive Packet Length register (USBRxPLen - 0x4002 0020)
9.10.3.4 USB Transmit Packet Length register (USBTxPLen - 0x4002 0024)
writing this register, the data is written to the selected endpoint buffer. The data is in little
endian format: the first byte sent on the USB bus will be the least significant byte of
USBTxData. USBTxData is a write only register.
Table 163. USB Transmit Data register (USBTxData - address 0x4002 001C) bit description
This gives the number of bytes remaining in the RAM for the current packet being
transferred and whether the packet is valid or not. This register will get updated at every
word that gets transferred to the system. The processor can use this register to get the
number of bytes to be transferred. When the number of bytes reaches zero, an end of
packet interrupt is generated.
Table 164. USB Receive Packet Length register (USBRxPlen - address 0x4002 0020) bit
This indicates the number of bytes still to be transferred from the processor to the RAM.
The processor has to program this register with the byte length of the packet to be sent,
before writing to the Transmit Data Register. The processor can read this register to
determine the number of bytes it has transferred to the memory.
Remark: To transfer an empty packet, this register has to be set to 0x00 and a single write
operation has to be performed on the Transmit Data Register.
Bit
31:0
Bit
9:0
10
31:11 -
Symbol
PKT_LNGTH -
DV
Symbol
TX_DATA
description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
-
Description
Transmit Data.
Rev. 2 — 7 July 2010
The remaining number of bytes to be read from the
currently selected endpoint’s buffer. When this field
decrements to 0, the RxENDPKT bit will be set in
USBDevIntSt.
Data valid. This bit is useful for isochronous endpoints.
Non-isochronous endpoints do not raise an interrupt when
an erroneous data packet is received. But invalid data
packet can be produced with a bus reset. For isochronous
endpoints, data transfer will happen even if an erroneous
packet is received. In this case DV bit will not be set for the
packet.
Data is invalid.
Data is valid.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 9: LPC13xx USB device controller
UM10375
© NXP B.V. 2010. All rights reserved.
Reset value
0x0000 0000
137 of 333
Reset
value
0
0
NA