LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 20

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
3.5.10 System reset status register
3.5.11 System PLL clock source select register
The SYSRSTSTAT register shows the source of the latest reset event. The bits are
cleared by writing a one to any of the bits. The POR event clears all other bits in this
register, but if another reset signal (e.g., EXTRST) remains asserted after the POR signal
is negated, then its bit is set to detected.
Table 15.
This register selects the clock source for the system PLL. The SYSPLLCLKUEN register
(see
Remark: The system oscillator must be selected if the system PLL is used to generate a
48 MHz clock to the USB block.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Bit
0
1
2
3
4
31:5
Section
Symbol
POR
EXTRST
WDT
BOD
SYSRST
-
System reset status register (SYSRESSTAT, address 0x4004 8030) bit description
3.5.12) must be toggled from LOW to HIGH for the update to take effect.
All information provided in this document is subject to legal disclaimers.
Value
0
1
0
1
0
1
0
1
0
1
-
Rev. 2 — 7 July 2010
Description
POR reset status
No POR detected
POR detected
Status of the external RESET pin
No RESET event detected
RESET detected
Status of the Watchdog reset
No WDT reset detected
WDT reset detected
Status of the Brown-out detect reset
No BOD reset detected
BOD reset detected
Status of the software system reset. The ARM software
reset has the same effect as the hardware reset using the
RESET pin.
No System reset detected
System reset detected
Reserved
Chapter 3: LPC13xx System configuration
UM10375
© NXP B.V. 2010. All rights reserved.
21 of 333
Reset
value
0x0
0x0
0x0
0x0
0x0
0x00