LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 255

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
Table 251. External Match Register (TMR16B0EMR - address 0x4000 C03C and TMR16B1EMR - address
Table 252. External match control
UM10375
User manual
Bit
0
1
2
3
5:4
7:6
9:8
11:10
31:12
EMR[11:10], EMR[9:8],
EMR[7:6], or EMR[5:4]
Symbol
EM0
EM1
EM2
EM3
EMC0
EMC1
EMC2
EMC3
-
0x4001 003C) bit description
14.8.11 Count Control Register (TMR16B0CTCR and TMR16B1CTCR)
00
01
10
11
Description
External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0,
whether or not this output is connected to its pin. When a match occurs between the TC
and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control
the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins
if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1,
whether or not this output is connected to its pin. When a match occurs between the TC
and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control
the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins
if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
External Match 2. This bit reflects the state of output CT16B0_MAT2 or match channel 2,
whether or not this output is connected to its pin. When a match occurs between the TC
and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control
the functionality of this output. This bit is driven to the CT16B1_MAT0 pins if the match
function is selected in the IOCON registers (0 = LOW, 1 = HIGH). Note that on
counter/timer 0 this match channel is not pinned out.
External Match 3. This bit reflects the state of output of match channel 3. When a match
occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do
nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin
available for this channel on either of the 16-bit timers.
External Match Control 0. Determines the functionality of External Match 0.
shows the encoding of these bits.
External Match Control 1. Determines the functionality of External Match 1.
shows the encoding of these bits.
External Match Control 2. Determines the functionality of External Match 2.
shows the encoding of these bits.
External Match Control 3. Determines the functionality of External Match 3.
shows the encoding of these bits.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edge(s) for counting.
Function
Do Nothing.
Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if
pinned out).
Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if
pinned out).
Toggle the corresponding External Match bit/output.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Chapter 14: LPC13xx 16-bit timer/counters (CT16B0/1)
Table 252
Table 252
Table 252
Table 252
UM10375
© NXP B.V. 2010. All rights reserved.
Reset
value
0
0
0
0
00
00
00
00
NA
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