LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 197

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
Table 216. I2SCLL + I2SCLH values for selected I
UM10375
User manual
I
Standard mode
Fast-mode
Fast-mode Plus
2
C mode
12.8.6 I
12.8.7 I
I2SCLL and I2SCLH values should not necessarily be the same. Software can set
different duty cycles on SCL by setting these two registers. For example, the I
specification defines the SCL low time and high time at different values for a Fast-mode
and Fast-mode Plus I
The I2CONCLR registers control clearing of bits in the I2CON register that controls
operation of the I
corresponding bit in the I
Table 217. I
AAC is the Assert Acknowledge Clear bit. Writing a 1 to this bit clears the AA bit in the
I2CONSET register. Writing 0 has no effect.
SIC is the I
register. Writing 0 has no effect.
STAC is the START flag Clear bit. Writing a 1 to this bit clears the STA bit in the
I2CONSET register. Writing 0 has no effect.
I2ENC is the I
I2CONSET register. Writing 0 has no effect.
This register controls the Monitor mode which allows the I
the I
400 kHz
1 MHz
I
frequency
100 kHz
Bit
1:0
2
3
4
5
6
7
31:8 -
2
2
2
C bit
C Control Clear register (I2C0CONCLR - 0x4000 0018)
C Monitor mode control register (I2C0MMCTRL - 0x4000 001C)
2
C bus without actually participating in traffic or interfering with the I
Symbol
-
AAC
SIC
-
STAC
I2ENC
-
2
2
C Interrupt Clear bit. Writing a 1 to this bit clears the SI bit in the I2CONSET
C Control Clear register (I2C0CONCLR - 0x4000 0018) bit description
6
60
15
-
2
C Interface Disable bit. Writing a 1 to this bit clears the I2EN bit in the
All information provided in this document is subject to legal disclaimers.
Description
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Assert acknowledge Clear bit.
I
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
START flag Clear bit.
I
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Reserved. The value read from a reserved bit is not defined.
2
2
2
C interrupt Clear bit.
C interface Disable bit.
C interface. Writing a one to a bit of this register causes the
8
80
20
8
2
C.
Rev. 2 — 7 July 2010
2
2
C clock values
C control register to be cleared. Writing a zero has no effect.
10
100
25
10
120
30
12
12
16
160
40
16
I2SCLH + I2SCLL
PCLK_I2C (MHz)
Chapter 12: LPC13xx I2C-bus controller
20
200
50
20
300
75
30
30
2
C module to monitor traffic on
40
400
100
40
50
500
125
50
UM10375
© NXP B.V. 2010. All rights reserved.
2
C bus.
60
600
150
60
2
C-bus
Reset
value
NA
0
NA
0
0
NA
-
199 of 333
70
700
175
70