LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 259

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
14.10 Architecture
UM10375
User manual
The block diagram for counter/timer0 and counter/timer1 is shown in
Fig 48. 16-bit counter/timer block diagram
MATn[2:0]
INTERRUPT
CAP0
STOP ON MATCH
RESET ON MATCH
LOAD[3:0]
All information provided in this document is subject to legal disclaimers.
CAPTURE CONTROL REGISTER
EXTERNAL MATCH REGISTER
MATCH CONTROL REGISTER
INTERRUPT REGISTER
CAPTURE REGISTER 0
TIMER CONTROL REGISTER
MATCH REGISTER 0
MATCH REGISTER 1
MATCH REGISTER 2
MATCH REGISTER 3
CONTROL
Rev. 2 — 7 July 2010
reset
Chapter 14: LPC13xx 16-bit timer/counters (CT16B0/1)
enable
CSN
MAXVAL
=
PRESCALE REGISTER
PRESCALE COUNTER
TIMER COUNTER
=
=
Figure
CE
UM10375
TCI
© NXP B.V. 2010. All rights reserved.
=
48.
PCLK
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