LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 283

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
18.5 Clocking and power control
18.6 Register description
Table 278. Register overview: ADC (base address 0x4001 C000)
[1]
UM10375
User manual
Name
AD0CR
AD0GDR
-
AD0INTEN R/W
AD0DR0
AD0DR1
AD0DR2
AD0DR3
AD0DR4
AD0DR5
AD0DR6
AD0DR7
AD0STAT
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Access Address
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
The peripheral clock to the ADC (PCLK) is provided by the system clock (see
This clock can be disabled through bit 13 in the SYSAHBCLKCTRL register
power savings.
The ADC can be powered down at run-time using the PDRUNCFG register
Basic clocking for the A/D converters is determined by the peripheral ADC clock PCLK. A
programmable divider is included in each converter to scale this clock to the 4.5 MHz
(max) clock needed by the successive approximation process. An accurate conversion
requires 11 clock cycles.
The ADC contains registers organized as shown in
Description
A/D Control Register. The AD0CR register must be written to select the
operating mode before A/D conversion can occur.
A/D Global Data Register. Contains the result of the most recent A/D
conversion.
Reserved.
A/D Interrupt Enable Register. This register contains enable bits that allow
the DONE flag of each A/D channel to be included or excluded from
contributing to the generation of an A/D interrupt.
A/D Channel 0 Data Register. This register contains the result of the most
recent conversion completed on channel 0
A/D Channel 1 Data Register. This register contains the result of the most
recent conversion completed on channel 1.
A/D Channel 2 Data Register. This register contains the result of the most
recent conversion completed on channel 2.
A/D Channel 3 Data Register. This register contains the result of the most
recent conversion completed on channel 3.
A/D Channel 4 Data Register. This register contains the result of the most
recent conversion completed on channel 4.
A/D Channel 5 Data Register. This register contains the result of the most
recent conversion completed on channel 5.
A/D Channel 6 Data Register. This register contains the result of the most
recent conversion completed on channel 6.
A/D Channel 7 Data Register. This register contains the result of the most
recent conversion completed on channel 7.
A/D Status Register. This register contains DONE and OVERRUN flags for
all of the A/D channels, as well as the A/D interrupt flag.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Chapter 18: LPC13xx Analog-to-Digital Converter (ADC)
Table
278.
UM10375
© NXP B.V. 2010. All rights reserved.
(Table
(Table
Reset
Value
0x0000 0000
NA
-
0x0000 0100
NA
NA
NA
NA
NA
NA
NA
NA
0
Figure
285 of 333
[1]
23) for
52).
3).