LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 14

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
Table 5.
UM10375
User manual
Name
-
PIOPORCAP0
PIOPORCAP1
-
BODCTRL
-
SYSTCKCAL
-
STARTAPRP0
STARTERP0
STARTRSRP0CLR
STARTSRP0
STARTAPRP1
STARTERP1
STARTRSRP1CLR
STARTSRP1
-
PDSLEEPCFG
PDAWAKECFG
PDRUNCFG
-
DEVICE_ID
Register overview: system control block (base address 0x4004 8000)
3.5.1 System memory remap register
Access
-
R
R
-
R/W
-
R/W
-
R/W
R/W
W
R
R/W
R/W
W
R
-
R/W
R/W
R/W
-
R
The system memory remap register selects whether the ARM interrupt vectors are read
from the boot ROM, the flash, or the SRAM.
Address offset Description
0x0EC - 0x0FC
0x100
0x104
0x108 - 0x14C
0x150
0x154
0x158
0x15C - 0x1FC
0x200
0x204
0x208
0x20C
0x210
0x214
0x218
0x21C
0x220 - 0x22C
0x230
0x234
0x238
0x23C - 0x3F0
0x3F4
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
POR captured PIO status 0
POR captured PIO status 1
Reserved
BOD control
Reserved
Reserved
Start logic edge control register 0; bottom
32 interrupts
Start logic signal enable register 0;
bottom 32 interrupts
interrupts
interrupts
Start logic edge control register 1; top 8
interrupts
Start logic signal enable register 1; top 8
interrupts
interrupts
Start logic status register 1; top 8
interrupts
Reserved
Power-down states in Deep-sleep mode
Power-down states after wake-up from
Deep-sleep mode
Power-down configuration register
Reserved
Reserved
System tick counter calibration
Start logic reset register 0; bottom 32
Start logic status register 0; bottom 32
Start logic reset register 1; top 8
Device ID
Chapter 3: LPC13xx System configuration
…continued
Reset value
-
User
dependent
User
dependent
0x0000 0000
0x0000 0000
-
0x0000 0004
-
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
-
0x0000 0000
0x0000 FDF0
0x0000 FDF0
-
part
dependent
UM10375
© NXP B.V. 2010. All rights reserved.
Reference
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Table 37
Table 37
-
Table 39
-
Table 40
-
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Table 48
-
Table 50
Table 51
Table 52
-
Table 53
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