C8051F131R Silicon Labs, C8051F131R Datasheet - Page 349

• Manufacturer Part Number: C8051F131R
• Description: 8-bit Microcontrollers - MCU 128kB 100MIPS 8448B RAM
• Manufacturer: Silicon Labs

Specifications of C8051F131R

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8.25 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 9
• Data Rom Size: 64 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

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Revision 1.3 to Revision 1.4
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OCUMENT
Added new paragraph tags: SFR Definition and JTAG Register Definition.
Product Selection Guide Table 1.1: Added RoHS-compliant ordering information.
Overview Chapter, Figure 1.8, “On-Chip Memory Map”: Corrected on-chip XRAM size to “8192 Bytes”.
SAR8 Chapter: Table 7.1, “ADC2 Electrical Characteristics”: Track/Hold minimum spec corrected to
“300 ns”.
SAR8 Chapter: Table 7.1, “ADC2 Electrical Characteristics”: Total Harmonic Distortion typical spec
corrected to “-51 dB”.
Oscillators Chapter, Figure 14.1, “Oscillator Diagram”: Corrected location of IOSCEN arrow.
CIP51 Chapter,
cycle instruction.
CIP51 Chapter, Interrupt Summary Table: Added “SFRPAGE” column and SFRPAGE value for each
interrupt source.
CIP-51 Chapter, Figure 11.2, “Memory Map”: Corrected on-chip XRAM size to “8192 Bytes”.
Port I/O Chapter, Crossbar Priority Figures: Character formatting problem corrected.
Port I/O Chapter, P7MDOUT Register Description: Removed references to UART and SMBus periph-
erals.
Port I/O Chapter, P3MDOUT Register Description: Corrected text to read “P3MDOUT.[7:0]”.
Timers Chapter: References to “TnCON” corrected to read “TMRnCN”.
PCA0 Chapter, Section 24.1: Added note about PCA0CN Register and effects of read-modify-write
instructions on the CF bit.
C
Section 11.3
HANGE
L
: Added note describing EA change behavior when followed by single-
IST
Rev. 1.4
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
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