C8051F131R Silicon Labs, C8051F131R Datasheet - Page 217

• Manufacturer Part Number: C8051F131R
• Description: 8-bit Microcontrollers - MCU 128kB 100MIPS 8448B RAM
• Manufacturer: Silicon Labs

Specifications of C8051F131R

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8.25 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 9
• Data Rom Size: 64 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

Bit 7:
Bits 6–0: CHMSCTH: Cache Miss Penalty Accumulator (bits 11–5)
Bit 7–1:
Bit 0:
CHMSOV
Bit7
Bit7
R
R
-
CHMSOV: Cache Miss Penalty Overflow.
This bit indicates when the Cache Miss Penalty Accumulator has overflowed since it was
last written.
0: The Cache Miss Penalty Accumulator has not overflowed since it was last written.
1: An overflow of the Cache Miss Penalty Accumulator has occurred since it was last written.
These are bits 11-5 of the Cache Miss Penalty Accumulator. The next four bits (bits 4-1) are
stored in CHMSCTL in the CCH0TN register.
The Cache Miss Penalty Accumulator is incremented every clock cycle that the processor is
delayed due to a cache miss. This is primarily used as a diagnostic feature, when optimizing
code for execution speed.
Writing to CHMSCTH clears the lower 5 bits of the Cache Miss Penalty Accumulator.
Reading from CHMSCTH returns the current value of CHMSTCH, and latches bits 4-1 into
CHMSTCL so that they can be read. Because bit 0 of the Cache Miss Penalty Accumulator
is not available, the Cumulative Miss Penalty is equal to 2 * (CCHMSTCH:CCHMSTCL).
Reserved.
FLBUSY: Flash Busy
This bit indicates when a Flash write or erase operation is in progress.
0: Flash is idle or reading.
1: Flash write/erase operation is currently in progress.
SFR Definition 16.4. CCH0MA: Cache Miss Accumulator
R/W
R/W
Bit6
Bit6
-
SFR Definition 16.5. FLSTAT: Flash Status
R/W
R/W
Bit5
Bit5
-
R/W
R/W
Bit4
Bit4
-
CHMSCTH
Rev. 1.4
R/W
R/W
Bit3
Bit3
-
C8051F120/1/2/3/4/5/6/7
R/W
R/W
Bit2
Bit2
-
C8051F130/1/2/3
R/W
R/W
Bit1
Bit1
-
SFR Address:
SFR Address:
FLBUSY 00000000
SFR Page:
SFR Page:
R/W
R/W
Bit0
Bit0
0x9A
F
0x88
F
00000000
Addressable
Reset Value
Reset Value
Bit
217