C8051F131R Silicon Labs, C8051F131R Datasheet - Page 162

• Manufacturer Part Number: C8051F131R
• Description: 8-bit Microcontrollers - MCU 128kB 100MIPS 8448B RAM
• Manufacturer: Silicon Labs

Specifications of C8051F131R

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8.25 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 9
• Data Rom Size: 64 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
162
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
Bit7
-
UNUSED. Read = 0b, Write = don't care.
ES1: UART1 Interrupt Priority Control.
This bit sets the priority of the UART1 interrupt.
0: UART1 interrupt set to low priority.
1: UART1 interrupt set to high priority.
UNUSED. Read = 0b, Write = don't care.
PADC2: ADC2 End Of Conversion Interrupt Priority Control.
This bit sets the priority of the ADC2 End of Conversion interrupt.
0: ADC2 End of Conversion interrupt set to low priority.
1: ADC2 End of Conversion interrupt set to high priority.
PWADC2: ADC2 Window Compare Interrupt Priority Control.
This bit sets the priority of the ADC2 Window Compare interrupt.
0: ADC2 Window Compare interrupt set to low priority.
1: ADC2 Window Compare interrupt set to high priority.
PT4: Timer 4 Interrupt Priority Control.
This bit sets the priority of the Timer 4 interrupt.
0: Timer 4 interrupt set to low priority.
1: Timer 4 interrupt set to high priority.
PADC0: ADC0 End of Conversion Interrupt Priority Control.
This bit sets the priority of the ADC0 End of Conversion Interrupt.
0: ADC0 End of Conversion interrupt set to low priority.
1: ADC0 End of Conversion interrupt set to high priority.
PT3: Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupts.
0: Timer 3 interrupt set to low priority.
1: Timer 3 interrupt set to high priority.
PS1
SFR Definition 11.17. EIP2: Extended Interrupt Priority 2
R/W
Bit6
R/W
Bit5
-
PADC2
R/W
Bit4
PWADC2
Rev. 1.4
R/W
Bit3
PT4
R/W
Bit2
PADC0
R/W
Bit1
SFR Address:
SFR Page:
PT3
R/W
Bit0
0xF7
All Pages
00000000
Reset Value