C8051F131R Silicon Labs, C8051F131R Datasheet - Page 328
![no-image](/images/no-image-200.jpg)
C8051F131R
Manufacturer Part Number
C8051F131R
Description
8-bit Microcontrollers - MCU 128kB 100MIPS 8448B RAM
Manufacturer
Silicon Labs
Datasheet
1.C8051F133R.pdf
(350 pages)
Specifications of C8051F131R
Product Category
8-bit Microcontrollers - MCU
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
100 MHz
Program Memory Size
128 KB
Data Ram Size
8.25 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Package / Case
TQFP-64
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
9
Data Rom Size
64 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
32
Number Of Timers
16 bit
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
500
Supply Voltage - Max
3.6 V
Supply Voltage - Min
3 V
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C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
24.2. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: Edge-triggered
Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit
Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP-
51 system controller. These registers are used to exchange data with a module and configure the module's
mode of operation.
Table 24.2 summarizes the bit settings in the PCA0CPMn registers used to select the PCA0 capture/com-
pare module’s operating modes. Setting the ECCFn bit in a PCA0CPMn register enables the module's
CCFn interrupt. Note: PCA0 interrupts must be globally enabled before individual CCFn interrupts are rec-
ognized. PCA0 interrupts are globally enabled by setting the EA bit (IE.7) and the EPCA0 bit (EIE1.3) to
logic 1. See Figure 24.3 for details on the PCA interrupt configuration.
328
Timer Overflow
PCA Counter/
W
M
P
1
6
n
PCA Module 0
PCA Module 1
PCA Module 2
PCA Module 3
PCA Module 4
PCA Module 5
(for n = 0 to 5)
PCA0CPMn
O
M
E
C
n
C
A
P
P
n
(CCF0)
(CCF1)
(CCF2)
(CCF3)
(CCF4)
(CCF5)
C
A
P
N
n
M
A
T
n
O
G
T
n
W
M
P
n
E
C
C
F
n
C
F
C
R
PCA0CN
C
C
F
5
C
C
F
4
C
C
F
3
Figure 24.3. PCA Interrupt Block Diagram
C
C
F
2
C
C
F
1
C
C
F
0
ECCF0
ECCF1
ECCF2
ECCF3
ECCF4
ECCF5
C
D
L
I
PCA0MD
C
P
S
2
C
P
S
1
0
1
0
1
0
1
0
1
0
1
0
1
C
P
S
0
E
C
F
0
1
Rev. 1.4
EPCA0
(EIE.3)
0
1
(IE.7)
EA
0
1
Interrupt
Priority
Decoder
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