C8051F131R Silicon Labs, C8051F131R Datasheet - Page 287

• Manufacturer Part Number: C8051F131R
• Description: 8-bit Microcontrollers - MCU 128kB 100MIPS 8448B RAM
• Manufacturer: Silicon Labs

Specifications of C8051F131R

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8.25 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 9
• Data Rom Size: 64 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

21. UART0
UART0 is an enhanced serial port with frame error detection and address recognition hardware. UART0
may operate in full-duplex asynchronous or half-duplex synchronous modes, and mutiproccessor commu-
nication is fully supported. Receive data is buffered in a holding register, allowing UART0 to start reception
of a second incoming data byte before software has finished reading the previous data byte. A Receive
Overrun bit indicates when new received data is latched into the receive buffer before the previously
received byte has been read.
UART0 is accessed via its associated SFR’s, Serial Control (SCON0) and Serial Data Buffer (SBUF0). The
single SBUF0 location provides access to both transmit and receive registers. Reading SCON0 accesses
the Receive register and writing SCON0 accesses the Transmit register.
UART0 may be operated in polled or interrupt mode. UART0 has two sources of interrupts: a Transmit
Interrupt flag, TI0 (SCON0.1) set when transmission of a data byte is complete, and a Receive Interrupt
flag, RI0 (SCON0.0) set when reception of a data byte is complete. UART0 interrupt flags are not cleared
by hardware when the CPU vectors to the interrupt service routine; they must be cleared manually by soft-
ware. This allows software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
Baud Rate Generation
F
E
0
R
X
O
V
0
UART0
C
O
T
X
L
0
Logic
SSTA0
S
M
O
D
0
C
S
0
T
L
K
1
S
0
T
C
L
K
1
S
R
C
K
0
L
1
R
C
S
0
L
K
1
Write to
SBUF0
Figure 21.1. UART0 Block Diagram
Tx Clock
Rx Clock
Stop Bit
Start
Start
Frame Error
Gen.
Detection
Load
SBUF0
D
TB80
CLR
SET
Q
Shift
S
M
0
0
SFR Bus
SBUF0
M
S
1
0
Rx Control
Tx Control
M
S
2
0
SCON0
Shift
Input Shift Register
EN
R
E
N
0
Zero Detector
T
B
8
0
SFR Bus
SBUF0
R
B
8
0
(9 bits)
Tx IRQ
Rev. 1.4
T
0
I
SBUF0
Rx IRQ
Read
R
0
I
0x1FF
Match Detect
C8051F120/1/2/3/4/5/6/7
Address
Match
SBUF
Send
Data
Load
TI0
RI0
RB80
SADDR0
SADEN0
RX0
C8051F130/1/2/3
TX0
Crossbar
Crossbar
(UART0) Interrupt
Serial Port
Port I/O
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