C8051F131R Silicon Labs, C8051F131R Datasheet - Page 163

• Manufacturer Part Number: C8051F131R
• Description: 8-bit Microcontrollers - MCU 128kB 100MIPS 8448B RAM
• Manufacturer: Silicon Labs

Specifications of C8051F131R

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8.25 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 9
• Data Rom Size: 64 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

11.4. Power Management Modes
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode
halts the CPU while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is
halted, all interrupts and timers (except the Missing Clock Detector) are inactive, and the system clock is
stopped. Since clocks are running in Idle mode, power consumption is dependent upon the system clock
frequency and the number of peripherals left in active mode before entering Idle. Stop mode consumes the
least power. SFR Definition 11.18 describes the Power Control Register (PCON) used to control the CIP-
51's power management modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power
management of the entire MCU is better accomplished by enabling/disabling individual peripherals as
needed. Each analog peripheral can be disabled when not in use and put into low power mode. Digital
peripherals, such as timers or serial buses, draw little power whenever they are not in use. Turning off the
Flash memory saves power, similar to entering Idle mode. Turning off the oscillator saves even more
power, but requires a reset to restart the MCU.
11.4.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes.
data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt or RST is asserted. The assertion of an enabled inter-
rupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume operation. The
pending interrupt will be serviced and the next instruction to be executed after the return from interrupt
(RETI) will be the instruction immediately following the one that set the Idle Mode Select bit. If Idle mode is
terminated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins pro-
gram execution at address 0x00000.
If enabled, the WDT will eventually cause an internal watchdog reset and thereby terminate the Idle mode.
This feature protects the system from an unintended permanent shutdown in the event of an inadvertent
write to the PCON register. If this behavior is not desired, the WDT may be disabled by software prior to
entering the Idle mode if the WDT was initially configured to allow this operation. This provides the oppor-
tunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for
an external stimulus to wake up the system. Refer to
figuration of the WDT.
Note: Any instruction which sets the IDLE bit should be immediately followed by an instruction which has
two or more opcode bytes. For example:
// in ‘C’:
PCON |= 0x01;
PCON = PCON;
; in assembly:
ORL PCON, #01h
MOV PCON, PCON
If the instruction following the write to the IDLE bit is a single-byte instruction and an interrupt occurs during
the execution of the instruction of the instruction which sets the IDLE bit, the CPU may not wake from IDLE
mode when a future interrupt occurs.
// Set IDLE bit
// ... Followed by a 3-cycle Dummy Instruction
; Set IDLE bit
; ... Followed by a 3-cycle Dummy Instruction
All internal registers and memory maintain their original
Rev. 1.4
Section 13
C8051F120/1/2/3/4/5/6/7
for more information on the use and con-
C8051F130/1/2/3
163