C8051F131R Silicon Labs, C8051F131R Datasheet - Page 259

• Manufacturer Part Number: C8051F131R
• Description: 8-bit Microcontrollers - MCU 128kB 100MIPS 8448B RAM
• Manufacturer: Silicon Labs

Specifications of C8051F131R

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8.25 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 9
• Data Rom Size: 64 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

19. System Management Bus / I2C Bus (SMBus0)
The SMBus0 I/O interface is a two-wire, bi-directional serial bus. SMBus0 is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus0 interface autonomously control-
ling the serial transfer of the data. A method of extending the clock-low duration is available to accommo-
date devices with different speed capabilities on the same bus.
SMBus0 may operate as a master and/or slave, and may function on a bus with multiple masters. SMBus0
provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic,
and START/STOP control and generation.
SMBUS
IRQ
S
L
V
6
S
L
V
5
SMB0ADR
S
L
V
4
B
U
S
Y
Interrupt
Request
B
S
L
V
3
E
N
S
M
B
S
V
7
L
2
SMB0CN
S
T
A
A
S
L
V
1
O
S
T
S
L
V
0
S
I
G
C
A
A
F
T
E
B
O
T
E
SFR Bus
0000000b
SMBUS CONTROL LOGIC
Arbitration
SCL Synchronization
Status Generation
SCL Generation (Master Mode)
IRQ Generation
A
7 MSBs
S
T
A
7
Figure 19.1. SMBus0 Block Diagram
SFR Bus
S
T
A
6
SMB0STA
S
T
A
5
S
T
A
4
8
S
T
A
3
SMB0DAT
S
A
T
2
Read
S
T
A
1
7
S
T
A
0
6
8
SMB0DAT
5
4
C
R
7
3
C
R
6
Clock Divide
Data Path
8
Control
2
SMB0CR
C
R
5
Logic
1
SMB0DAT
Rev. 1.4
C
R
4
Write to
0
C
R
3
C
R
2
C
R
1
Control
C8051F120/1/2/3/4/5/6/7
C
R
0
SDA
Control
SCL
1
0
SYSCLK
FILTER
FILTER
C8051F130/1/2/3
N
N
SDA
SCL
C
R
O
S
S
B
A
R
Port I/O
259