C8051F131R Silicon Labs, C8051F131R Datasheet - Page 247

• Manufacturer Part Number: C8051F131R
• Description: 8-bit Microcontrollers - MCU 128kB 100MIPS 8448B RAM
• Manufacturer: Silicon Labs

Specifications of C8051F131R

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8.25 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 9
• Data Rom Size: 64 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
WEAKPUD XBARE CNVST2E
R/W
Bit7
WEAKPUD: Weak Pullup Disable Bit.
0: Weak pullups globally enabled.
1: Weak pullups globally disabled.
XBARE: Crossbar Enable Bit.
0: Crossbar disabled. All pins on Ports 0, 1, 2, and 3, are forced to Input mode.
1: Crossbar enabled.
CNVST2E: External Convert Start 2 Input Enable Bit.
0: CNVSTR2 unavailable at Port pin.
1: CNVSTR2 routed to Port pin.
T4EXE: T4EX Input Enable Bit.
0: T4EX unavailable at Port pin.
1: T4EX routed to Port pin.
T4E: T4 Input Enable Bit.
0: T4 unavailable at Port pin.
1: T4 routed to Port pin.
UART1E: UART1 I/O Enable Bit.
0: UART1 I/O unavailable at Port pins.
1: UART1 TX and RX routed to 2 Port pins.
EMIFLE: External Memory Interface Low-Port Enable Bit.
0: P0.7, P0.6, and P0.5 functions are determined by the Crossbar or the Port latches.
1: If EMI0CF.4 = ‘0’ (External Memory Interface is in Multiplexed mode)
1: If EMI0CF.4 = ‘1’ (External Memory Interface is in Non-multiplexed mode)
CNVST0E: ADC0 External Convert Start Input Enable Bit.
0: CNVST0 for ADC0 unavailable at Port pin.
1: CNVST0 for ADC0 routed to Port pin.
SFR Definition 18.3. XBR2: Port I/O Crossbar Register 2
R/W
Bit6
P0.7 (/WR), P0.6 (/RD), and P0.5 (ALE) are ‘skipped’ by the Crossbar and their
output states are determined by the Port latches and the External Memory Interface.
P0.7 (/WR) and P0.6 (/RD) are ‘skipped’ by the Crossbar and their output states are
determined by the Port latches and the External Memory Interface.
R/W
Bit5
T4EXE
R/W
Bit4
Rev. 1.4
T4E
R/W
Bit3
C8051F120/1/2/3/4/5/6/7
UART1E
R/W
Bit2
C8051F130/1/2/3
EMIFLE CNVST0E 00000000
R/W
Bit1
SFR Address:
SFR Page:
R/W
Bit0
0xE3
F
Reset Value
247