C8051F131R Silicon Labs, C8051F131R Datasheet - Page 299

• Manufacturer Part Number: C8051F131R
• Description: 8-bit Microcontrollers - MCU 128kB 100MIPS 8448B RAM
• Manufacturer: Silicon Labs

Specifications of C8051F131R

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8.25 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 9
• Data Rom Size: 64 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

22. UART1
UART1 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in
UART1 to start reception of a second incoming data byte before software has finished reading the previous
data byte.
UART1 has two associated SFRs: Serial Control Register 1 (SCON1) and Serial Data Buffer 1 (SBUF1).
The single SBUF1 location provides access to both transmit and receive registers. Reading SBUF1
accesses the buffered Receive register; writing SBUF1 accesses the Transmit register.
With UART1 interrupts enabled, an interrupt is generated each time a transmit is completed (TI1 is set in
SCON1), or a data byte has been received (RI1 is set in SCON1). The UART1 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART1 interrupt (transmit complete or receive
complete).
Section “22.1. Enhanced Baud Rate Generation” on page 300
Rate Generator
UART1 Baud
Write to
SBUF1
Figure 22.1. UART1 Block Diagram
Rx Clock
Tx Clock
Stop Bit
Start
Start
SBUF1
Read
SCON1
TB81
D
SET
CLR
Shift
Input Shift Register
Q
Shift
SFR Bus
(RX Latch)
SBUF1
Tx Control
Rx Control
(9 bits)
0x1FF
SFR Bus
Zero Detector
(TX Shift)
SBUF1
RB81
Rev. 1.4
Load SBUF1
Rx IRQ
Tx IRQ
TI1
RI1
SBUF1
C8051F120/1/2/3/4/5/6/7
Load
Send
Data
Interrupt
Serial
Port
RX1
TX1
C8051F130/1/2/3
). Received data buffering allows
Crossbar
Crossbar
Port I/O
299