C8051F131R Silicon Labs, C8051F131R Datasheet - Page 10

• Manufacturer Part Number: C8051F131R
• Description: 8-bit Microcontrollers - MCU 128kB 100MIPS 8448B RAM
• Manufacturer: Silicon Labs

Specifications of C8051F131R

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8.25 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 9
• Data Rom Size: 64 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
6. ADC0 (10-Bit ADC, C8051F122/3/6/7 and C8051F13x Only)
7. ADC2 (8-Bit ADC, C8051F12x Only)
8. DACs, 12-Bit Voltage Mode (C8051F12x Only)
9. Voltage Reference
10. Comparators
11. CIP-51 Microcontroller
12. Multiply And Accumulate (MAC0)
10
Figure 6.1. 10-Bit ADC0 Functional Block Diagram ................................................. 73
Figure 6.2. Typical Temperature Sensor Transfer Function..................................... 74
Figure 6.3. ADC0 Track and Conversion Example Timing....................................... 76
Figure 6.4. ADC0 Equivalent Input Circuits.............................................................. 77
Figure 6.5. ADC0 Data Word Example .................................................................... 83
Figure 6.6. 10-Bit ADC0 Window Interrupt Example:
Figure 6.7. 10-Bit ADC0 Window Interrupt Example:
Figure 6.8. 10-Bit ADC0 Window Interrupt Example:
Figure 6.9. 10-Bit ADC0 Window Interrupt Example:
Figure 7.1. ADC2 Functional Block Diagram............................................................ 91
Figure 7.2. ADC2 Track and Conversion Example Timing....................................... 93
Figure 7.3. ADC2 Equivalent Input Circuit................................................................ 94
Figure 7.4. ADC2 Data Word Example .................................................................... 99
Figure 7.5. ADC2 Window Compare Examples, Single-Ended Mode.................... 100
Figure 7.6. ADC2 Window Compare Examples, Differential Mode ........................ 101
Figure 8.1. DAC Functional Block Diagram............................................................ 105
Figure 9.1. Voltage Reference Functional Block Diagram (C8051F120/2/4/6) ...... 114
Figure 9.2. Voltage Reference Functional Block Diagram (C8051F121/3/5/7) ...... 115
Figure 9.3. Voltage Reference Functional Block Diagram (C8051F130/1/2/3) ...... 117
Figure 10.1. Comparator Functional Block Diagram .............................................. 119
Figure 10.2. Comparator Hysteresis Plot ............................................................... 121
Figure 11.1. CIP-51 Block Diagram....................................................................... 128
Figure 11.2. Memory Map ...................................................................................... 133
Figure 11.3. Address Memory Map for Instruction Fetches (128 kB Flash Only)... 134
Figure 11.4. SFR Page Stack................................................................................. 137
Figure 11.5. SFR Page Stack While Using SFR Page 0x0F To Access Port 5...... 138
Figure 11.6. SFR Page Stack After ADC2 Window Comparator Interrupt Occurs . 139
Figure 11.7. SFR Page Stack Upon PCA Interrupt Occurring During an ADC2 ISR 140
Figure 11.8. SFR Page Stack Upon Return From PCA Interrupt ........................... 140
Figure 11.9. SFR Page Stack Upon Return From ADC2 Window Interrupt ........... 141
Figure 12.1. MAC0 Block Diagram ......................................................................... 165
Figure 12.2. Integer Mode Data Representation .................................................... 166
Figure 12.3. Fractional Mode Data Representation................................................ 166
Figure 12.4. MAC0 Pipeline.................................................................................... 167
Right Justified Single-Ended Data ......................................................... 86
Right Justified Differential Data ............................................................. 87
Left Justified Single-Ended Data ........................................................... 88
Left Justified Differential Data................................................................ 89
Rev. 1.4