C8051F131R Silicon Labs, C8051F131R Datasheet - Page 329

• Manufacturer Part Number: C8051F131R
• Description: 8-bit Microcontrollers - MCU 128kB 100MIPS 8448B RAM
• Manufacturer: Silicon Labs

Specifications of C8051F131R

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8.25 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 9
• Data Rom Size: 64 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

24.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes PCA0 to capture the value of the PCA0 counter/
timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn
bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and
must be cleared by software.
Note: The signal at CEXn must be high or low for at least 2 system clock cycles in order to be valid.
PWM16 ECOM CAPP CAPN
Table 24.2. PCA0CPM Register Settings for PCA Capture/Compare Modules
Port I/O
X
X
X
X
X
X
0
1
X = Don’t Care
X
X
X
1
1
1
1
1
Crossbar
0
1
0
0
0
0
0
1
Figure 24.4. PCA Capture Mode Diagram
CEXn
0
0
0
0
0
0
1
1
MAT
0
0
0
1
1
0
0
0
TOG
W
P
M
1
6
n
0
0
0
0
1
1
0
0
PCA0CPMn
C
O
M
E
n
Rev. 1.4
C
A
P
P
n
C
A
P
N
n
0
1
M
A
T
n
PWM ECCF
O
G
T
n
0
0
0
0
0
1
1
1
W
P
M
n
C8051F120/1/2/3/4/5/6/7
C
C
E
F
n
0
1
X
X
X
X
X
X
0
0
C
F
C
R
PCA0CN
C
C
F
5
Capture triggered by positive edge
C
C
F
4
Capture triggered by transition on
PCA
Timebase
C
C
F
3
C8051F130/1/2/3
Capture triggered by negative
16-Bit Pulse Width Modulator
C
C
8-Bit Pulse Width Modulator
F
2
C
C
F
1
PCA Interrupt
C
C
F
0
High Speed Output
Frequency Output
Capture
Operation Mode
Software Timer
edge on CEXn
PCA0CPLn
PCA0L
on CEXn
CEXn
PCA0CPHn
PCA0H
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