C8051F131R Silicon Labs, C8051F131R Datasheet - Page 341
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C8051F131R
Manufacturer Part Number
C8051F131R
Description
8-bit Microcontrollers - MCU 128kB 100MIPS 8448B RAM
Manufacturer
Silicon Labs
Datasheet
1.C8051F133R.pdf
(350 pages)
Specifications of C8051F131R
Product Category
8-bit Microcontrollers - MCU
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
100 MHz
Program Memory Size
128 KB
Data Ram Size
8.25 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Package / Case
TQFP-64
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
9
Data Rom Size
64 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
32
Number Of Timers
16 bit
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
500
Supply Voltage - Max
3.6 V
Supply Voltage - Min
3 V
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25. JTAG (IEEE 1149.1)
Each MCU has an on-chip JTAG interface and logic to support boundary scan for production and in-sys-
tem testing, Flash read/write operations, and non-intrusive in-circuit debug. The JTAG interface is fully
compliant with the IEEE 1149.1 specification. Refer to this specification for detailed descriptions of the Test
Interface and Boundary-Scan Architecture. Access of the JTAG Instruction Register (IR) and Data Regis-
ters (DR) are as described in the Test Access Port and Operation of the IEEE 1149.1 specification.
The JTAG interface is accessed via four dedicated pins on the MCU: TCK, TMS, TDI, and TDO.
Through the 16-bit JTAG Instruction Register (IR), any of the eight instructions shown in Figure 25.1 can
be commanded. There are three DR’s associated with JTAG Boundary-Scan, and four associated with
Flash read/write operations on the MCU.
IR Value
0xFFFF
0x0000
0x0002
0x0004
0x0082
0x0083
0x0084 Flash Address
0x0085
Bit15
Flash Control
JTAG Register Definition 25.1. IR: JTAG Instruction Register
Instruction
Flash Scale
PRELOAD
Flash Data
SAMPLE/
EXTEST
IDCODE
BYPASS
Selects the Boundary Data Register for control and observability of all
device pins
Selects the Boundary Data Register for observability and presetting the
scan-path latches
Selects device ID Register
Selects Bypass Data Register
Selects FLASHCON Register to control how the interface logic responds
to reads and writes to the FLASHDAT Register
Selects FLASHDAT Register for reads and writes to the Flash memory
Selects FLASHADR Register which holds the address of all Flash read,
write, and erase operations
Selects FLASHSCL Register which controls the Flash one-shot timer and
read-always enable
Rev. 1.4
C8051F120/1/2/3/4/5/6/7
Description
C8051F130/1/2/3
Bit0
Reset Value
0x0000
341
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