DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 88

• Manufacturer Part Number: DS26528GNA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GNA4

• Part # Aliases: 90-26528-NA4

9.
Thirteen address bits are used to control the settings of the registers. The address map is compatible with the
Dallas Semiconductor octal framer product, DS26401, as well as the DS26521, DS26522, and DS26524.
The registers control functions of the framers, LIU, and BERT within the DS26528. The map is divided into eight
framers, followed by eight LIUs and eight BERTs. Global registers (applicable to all eight transceivers and BERTs)
are located within the address space of Framer 1.
The bulk write mode is a special mode to write all eight transceivers with one write command (see the
register).
The register details are provided in the following tables. The framer registers bits are provided for Framer 0, and
address bits A[11:8] determine the framer addressed.
9.1
Table 9-1. Register Address Ranges (in Hex)
CHANNEL
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
—
DEVICE REGISTERS
Register Listings
Figure 9-1
REGISTERS
00F0–00FF
GLOBAL
shows the register map.
—
—
—
—
—
—
—
—
0C00–0CEF
0A00–0AEF
0E00–0EEF
0000–00EF
0200–02EF
0400–04EF
0600–06EF
0800–08EF
RECEIVE
FRAMER
—
88 of 276
0D00–0DEF
0B00–0BEF
0F00–0FEF
TRANSMIT
0100–01EF
0300–03EF
0500–05EF
0700–07EF
0900–09EF
FRAMER
—
DS26528 Octal T1/E1/J1 Transceiver
10C0–10DF
10A0–10BF
10E0–10FF
1000–101F
1020–103F
1040–105F
1060–107F
1080–109F
LIU
—
1100–110F
1110–111F
1120–112F
1130–113F
1140–114F
1160–116F
1150–115F
1170–117F
BERT
—
GTCR1