DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 198

• Manufacturer Part Number: DS26528GNA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GNA4

• Part # Aliases: 90-26528-NA4

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: See
Bit 7: TFDL Register Select (TFDLS).
Bit 6: Transmit SLC-96 (TSLC96). Set this bit to a one in SLC-96 framing applications. Must be set to source the
SLC-96 alignment pattern and data from the
Bit 4: F-Bit Corruption Type 2 (FBCT2). Setting this bit high enables the corruption of one Ft (D4 framing mode)
or FPS (ESF framing mode) bit in every 128 Ft or FPS bits as long as the bit remains set.
Bit 3: F-Bit Corruption Type 1 (FBCT1). A low-to-high transition of this bit causes the next three consecutive Ft
(D4 framing mode) or FPS (ESF framing mode) bits to be corrupted causing the remote end to experience a loss of
synchronization.
Bit 2: Transmit D4 RAI Select (TD4RM).
Bit 1: Pulse Density Enforcer Enable (PDE). The framer always examines both the transmit and receive data
streams for violations of the following rules which are required by ANSI T1.403: no more than 15 consecutive zeros
and at least N ones in each and every time window of 8 x (N +1) bits where N = 1 through 23. Violations for the
transmit and receive data streams are reported in the TLS1.3 and RLS2.7 bits, respectively. When this bit is set to
one, the DS26528 will force the transmitted stream to meet this requirement no matter the content of the
transmitted stream. When running B8ZS, this bit should be set to zero since B8ZS-encoded data streams cannot
violate the pulse density requirements.
Bit 0: Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS).
0 = source FDL or Fs bits from the internal TFDL register or the SLC-96 data formatter (TCR2.6)
1 = source FDL or Fs bits from the internal HDLC controller
0 = SLC-96 insertion disabled
1 = SLC-96 insertion enabled
0 = zeros in bit 2 of all channels
1 = a one in the S-bit position of frame 12
0 = disable transmit pulse density enforcer
1 = enable transmit pulse density enforcer
0 = no stuffing occurs
1 = force bit 7 to a one as determined by the GB7S bit at TCR1.3
TCR2
TFDLS
for E1 mode.
7
0
TSLC96
TCR2 (T1 Mode)
Transmit Control Register 2
182h + (200h x n): where n = 0 to 7, for Ports 1 to 8
6
0
—
5
0
T1TSLC1:T1TSLC3
198 of 276
FBCT2
4
0
registers. See Section
FBCT1
3
0
DS26528 Octal T1/E1/J1 Transceiver
TD4RM
2
0
8.9.4.4
PDE
1
0
for details.
TB7ZS
0
0