DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 64

• Manufacturer Part Number: DS26528GNA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GNA4

• Part # Aliases: 90-26528-NA4

8.9.11 Transmit Per-Channel Idle Code Insertion
Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions.
The Transmit Idle Code Definition registers (TIDR1:TIDR32) are provided to set the 8-bit idle code for each
channel. The Transmit Channel Idle Code Enable registers (TCICE1:TCICE4) are used to enable idle code
replacement on a per-channel basis.
8.9.12 Receive Per-Channel Idle Code Insertion
Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. The
Receive Idle Code Definition registers (RIDR1:RIDR32) are provided to set the 8-bit idle code for each channel.
The Receive Channel Idle Code Enable registers (RCICE1:RCICE4) are used to enable idle code replacement on
a per-channel basis.
8.9.13 Per-Channel Loopback
The Per-Channel Loopback Enable registers (PCL1:PCL4) determine which channels (if any) from the backplane
should be replaced with the data from the receive side, i.e., off the T1 or E1 line. If this loopback is enabled, the
transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this would be to tie
RCLK to TCLK and RFSYNC to TSYNC. There are no restrictions on which channels can be looped back or on
how many channels can be looped back.
Each of the bit positions in the Per-Channel Loopback Enable registers (PCL1:PCL4) represents a DS0 channel in
the outgoing frame. When these bits are set to 1, data from the corresponding receive channel replaces the data
on
8.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)
The DS26528 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is
enabled, the data stream presented at TSER will already have the FAS/NFAS, CRC multiframe alignment word,
and CRC-4 checksum in time slot 0. The user can modify the Sa-bit positions and this change in data content will
be used to modify the CRC-4 checksum. This modification, however, does not corrupt any error information the
original CRC-4 checksum may contain. In this mode of operation, TSYNC must be configured to multiframe mode.
The data at TSER must be aligned to the TSYNC signal. If TSYNC is an input, the user must assert TSYNC
aligned at the beginning of the multiframe relative to TSER. If TSYNC is an output, the user must multiframe align
the data presented to TSER. This mode is enabled with the TCR3.0 control bit (CRC4R). Note that the E1
transmitter must already be enabled for CRC insertion with the TCR1.0 control bit (TCRC4).
Figure 8-8. CRC-4 Recalculate Method
TSER
TTIP/TRING
for that channel.
INSERT
NEW CRC-4
CODE
EXTRACT
OLD CRC-4
CODE
+
CRC-4
CALCULATOR
64 of 276
XOR
DS26528 Octal T1/E1/J1 Transceiver
NEW Sa-BIT
DATA
MODIFY
Sa-BIT
POSITIONS
TSER