DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 215

• Manufacturer Part Number: DS26528GNA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GNA4

• Part # Aliases: 90-26528-NA4

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Transmit Channel Blocking Channels 1 to 32 Control Bits (CH[1:32]).
*Note that TCBR4 has two functions:
0 = force the TCHBLK pin to remain low during this channel time
1 = force the TCHBLK pin high during this channel time
When 2.048MHz backplane mode is selected, this register allows the user to enable the channel blocking
signal for any of the 32 possible backplane channels.
When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not the
TCHBLK signal will pulse high during the F-bit time:
In this mode, TCBR4.1 to TCBR4.7 should be set to 0.
(MSB)
CH16
CH24
CH32
CH8
0
TCBR4.0 = 0: Do not pulse TCHBLK during the F-bit.
TCBR4.0 = 1: Pulse TCHBLK during the F-bit.
CH15
CH23
CH31
CH7
TCBR1, TCBR2, TCBR3, TCBR4
Transmit Channel Blocking Registers 1 to 4
1C4h, 1C5h, 1C6h, 1C7h + (200h x n): where n = 0 to 7, for Ports 1 to 8
0
CH14
CH22
CH30
CH6
0
CH13
CH21
CH29
CH5
0
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CH12
CH20
CH28
CH4
0
CH11
CH19
CH27
CH3
0
DS26528 Octal T1/E1/J1 Transceiver
CH10
CH18
CH26
CH2
0
(LSB)
(F-bit)
CH17
CH25
CH1
CH9
0
TCBR1
TCBR2
TCBR3
TCBR4*
(E1 Mode
Only)