DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 228

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DS26528GNA4

Manufacturer Part Number
DS26528GNA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS26528GNA4

Part # Aliases
90-26528-NA4
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: BERT Repetitive Pattern Set Bits 7 to 0 (RPAT[7:0]). RPAT0 is the LSB of the 32-bit repetitive
pattern.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: BERT Repetitive Pattern Set Bits 15 to 8 (RPAT[15:8]).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: BERT Repetitive Pattern Set Bits 23 to 16 (RPAT[23:16]).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: BERT Repetitive Pattern Set Bits 31 to 24 (RPAT[31:24]). RPAT31 is the MSB of the 32-bit
repetitive pattern.
RPAT15
RPAT23
RPAT31
RPAT7
7
0
7
0
7
0
7
0
RPAT14
RPAT22
RPAT30
BRP1
BERT Repetitive Pattern Set Register 1
1101h + (10h x n): where n = 0 to 7, for Ports 1 to 8
BRP2
BERT Repetitive Pattern Set Register 2
1102h + (10h x n): where n = 0 to 7, for Ports 1 to 8
BRP3
BERT Repetitive Pattern Set Register 3
1103h + (10h x n): where n = 0 to 7, for Ports 1 to 8
BRP4
BERT Repetitive Pattern Set Register 4
1104h + (10h x n): where n = 0 to 7, for Ports 1 to 8
RPAT6
6
0
6
0
6
0
6
0
RPAT13
RPAT21
RPAT29
RPAT5
5
0
5
0
5
0
5
0
RPAT12
RPAT20
RPAT28
RPAT4
228 of 276
4
0
4
0
4
0
4
0
RPAT11
RPAT19
RPAT27
RPAT3
3
0
3
0
3
0
3
0
DS26528 Octal T1/E1/J1 Transceiver
RPAT10
RPAT18
RPAT26
RPAT2
2
0
2
0
2
0
2
0
RPAT17
RPAT25
RPAT1
RPAT9
1
0
1
0
1
0
1
0
RPAT16
RPAT24
RPAT0
RPAT8
0
0
0
0
0
0
0
0

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