DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 2

• Manufacturer Part Number: DS26528GNA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GNA4

• Part # Aliases: 90-26528-NA4

1.
2.
3.
4.
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1.1
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
7.1
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.2.1
8.4.1
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.9.6
8.9.7
8.9.8
8.9.9
8.9.10
8.9.11
DETAILED DESCRIPTION.................................................................................................9
FEATURE HIGHLIGHTS ..................................................................................................10
APPLICATIONS ...............................................................................................................13
SPECIFICATIONS COMPLIANCE ...................................................................................14
ACRONYMS AND GLOSSARY .......................................................................................16
BLOCK DIAGRAMS.........................................................................................................17
PIN DESCRIPTIONS ........................................................................................................19
FUNCTIONAL DESCRIPTION .........................................................................................27
M
G
L
C
J
F
S
HDLC C
T
C
P
P
C
R
I
G
P
D
S
F
NITIALIZATION AND
ITTER
INE
RAMER
EST AND
RAMERS
YSTEM
IN
ROCESSOR
ER
YSTEM
LOCK
ONTROL
LOCK
ESETS AND
EVICE
ENERAL
LOBAL
AJOR
F
Backplane Clock Generation ............................................................................................................... 27
Example Device Initialization Sequence .............................................................................................. 30
-P
Elastic Stores ....................................................................................................................................... 32
IBO Multiplexer..................................................................................................................................... 35
H.100 (CT Bus) Compatibility .............................................................................................................. 42
Receive and Transmit Channel Blocking Registers............................................................................. 43
Transmit Fractional Support (Gapped Clock Mode) ............................................................................ 43
Receive Fractional Support (Gapped Clock Mode) ............................................................................. 43
T1 Framing........................................................................................................................................... 44
E1 Framing........................................................................................................................................... 47
T1 Transmit Synchronizer .................................................................................................................... 49
Signaling .............................................................................................................................................. 50
T1 Data Link......................................................................................................................................... 54
E1 Data Link......................................................................................................................................... 56
Maintenance and Alarms ..................................................................................................................... 57
E1 Automatic Alarm Generation .......................................................................................................... 60
Error-Count Registers .......................................................................................................................... 61
DS0 Monitoring Function...................................................................................................................... 63
Transmit Per-Channel Idle Code Insertion........................................................................................... 64
I
UNCTIONAL
NTERFACE
ORT
A
S
S
O
I
/F
R
I
ONTROLLERS
NTERRUPTS
B
TTENUATOR
YNTHESIZER
TRUCTURE
PERATING
NTERFACE
......................................................................................................................................10
......................................................................................................................................44
ESOURCES
D
P
ACKPLANE
ORMATTER
R
ORT
IAGNOSTICS
ESOURCES
I
P
NTERFACE
OWER
............................................................................................................................10
............................................................................................................................12
D
ESCRIPTION
C
.......................................................................................................................27
M
......................................................................................................................11
-D
.....................................................................................................................10
.....................................................................................................................30
ONFIGURATION
I
....................................................................................................................10
....................................................................................................................10
....................................................................................................................30
NTERFACE
ODES
...................................................................................................................12
OWN
................................................................................................................12
................................................................................................................27
................................................................................................................30
.............................................................................................................9
M
ODES
......................................................................................................19
TABLE OF CONTENTS
...................................................................................................32
..............................................................................................29
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DS26528 Octal T1/E1/J1 Transceiver