DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 24

• Manufacturer Part Number: DS26528GNA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GNA4

• Part # Aliases: 90-26528-NA4

NAME
WRB/
RDB/
RWB
INTB
CSB
DSB
BTS
A12
A11
A10
D7
D6
D5
D4
D3
D2
D1
D0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
M13
B10
A10
C10
PIN
M9
M8
C8
A8
B8
B9
A9
C9
D9
E9
N9
R8
P8
N8
R7
R9
F8
F9
T9
T8
L9
T7
TYPE
U
I
I
I
I
I
I
Address [12:0]. This bus selects a specific register in the DS26528 during
read/write access. A12 is the MSB and A0 is the LSB.
Data [7:0]. This 8-bit, bidirectional data bus is used for read/write access of the
DS26528 information and control registers. D7 is the MSB and D0 is the LSB.
Chip-Select Bar. This active-low signal is used to qualify register read/write
accesses. The RDB/DSB and WRB signals are qualified with CSB.
Read-Data Bar/Data-Strobe Bar. This active-low signal along with CSB qualifies
read access to one of the DS26528 registers. The DS26528 drives the data bus
with the contents of the addressed register while RDB and CSB are low.
Write-Read Bar/Read-Write Bar. This active-low signal along with CSB qualifies
write access to one of the DS26528 registers. Data at D[7:0] is written into the
addressed register at the rising edge of WRB while CSB is low.
Interrupt Bar. This active-low, open-drain output is asserted when an unmasked
interrupt event is detected. INTB will be deasserted when all interrupts have been
acknowledged and serviced. Extensive mask bits are provided at the global level,
framer, LIU, and BERT level.
Bus Type Select. Set high to select Motorola bus timing, low to select Intel bus
timing. This pin controls the function of the RDB/DSB and WRB pins.
MICROPROCESSOR INTERFACE
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FUNCTION
DS26528 Octal T1/E1/J1 Transceiver