DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 260

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DS26528GNA4

Manufacturer Part Number
DS26528GNA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS26528GNA4

Part # Aliases
90-26528-NA4
Figure 12-9. Transmit Formatter Timing, Elastic Store Enabled
Figure 12-10. BPCLK Timing
Figure 12-11. Transmit Formatter Timing—Line Side
NOTE 1: TSER IS ONLY SAMPLED ON THE FALLING EDGE OF TSYSCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED.
NOTE 2: TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TSYSCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED.
TTIP, TRING
TSYSCLK
TCHCLK
TCHBLK
TSSYNC
TCLK
TSER
T SSYN C IO
N otes:
1. TS S Y NC IO is configured as an O utput (G TC R 2.TS S Y N IO S E L = 1)
BPC LK
t D3
1
t D3
t SU
t D3
260 of 276
t
D 5
t
SU
t
HD
t HD
t
SL
t
CL
t
SP
DS26528 Octal T1/E1/J1 Transceiver
t
CP
t
SH
t
CH

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