DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 225

• Manufacturer Part Number: DS26528GNA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GNA4

• Part # Aliases: 90-26528-NA4

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 5 and 4: Receive Impedance Match 1 and 0 (RIMPM[1:0]). These bits are used to select the receive
impedance match value. These must be set according to the cable impedance. Even if the internal receive match
impedance is turned off (RIMPOFF); the external cable impedance must be specified for optimum operation by
RIMPM1 to 0. See
Bits 1 and 0: Receiver Sensitivity/Monitor Gain Select 1 and 0 (RSMS[1:0]). These bits are used to select the
receiver sensitivity level and additional gain in monitoring applications. The monitor mode (RMONEN) adds
resistive gain to compensate for the signal loss caused by the isolation resistors. See
Table 9-18. Receive Impedance Selection
Bit 7: Receive G.703 Clock Enable (RG703). If this bit is set, the receiver expects a 2.048MHz or 1.544MHz
clock from the RTIP/RRING, based on the selection of T1 (1.544) or E1 (2.048) mode in the
Bit 6: Receive Impedance Termination Off (RIMPOFF).
Bit 3: Receiver Turns Ratio (RTR).
Bit 2: Receiver Monitor Mode Enable (RMONEN).
RIMPM[1:0]
0 = Receive terminating impedance match is enabled.
1 = Receive terminating impedance match is disabled.
0 = Receive transformer turns ratio is 1:1.
1 = Receive transformer turns ratio is 2:1. This option should only be used in short-haul applications.
0 = Disable receive monitor mode.
1 = Enable receive monitor mode. Resistive gain is added with the maximum sensitivity. The receiver
sensitivity is determined by RSMS1 and RSMS0.
00
01
10
11
RG703
7
0
Table
RIMPOFF
9-18.
LRISMR
LIU Receive Impedance and Sensitivity Monitor Register
1007h + (20h x n): where n = 0 to 7, for Ports 1 to 8
RECEIVE IMPEDANCE
6
0
SELECTED (Ω)
100
110
120
75
RIMPM1
5
0
RIMPM0
225 of 276
4
0
RTR
3
0
DS26528 Octal T1/E1/J1 Transceiver
RMONEN
2
0
Table 9-19
LTRCR
RSMS1
1
0
and
register.
Table
RSMS0
9-20.
0
0