DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 71

• Manufacturer Part Number: DS26528GNA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GNA4

• Part # Aliases: 90-26528-NA4

8.10.2 Transmit HDLC Controller
8.10.2.1
The Transmit HDLC FIFO Buffer Available register (TFBA) indicates the number of bytes that can be written into
the transmit FIFO. The count from this register informs the host as to how many bytes can be written into the
transmit FIFO without overflowing the buffer. This is a real-time register. The count shall remain valid and stable
during the read cycle.
8.10.2.2
The HDLC status registers in the DS26528 allow for flexible software interface to meet the user’s preferences.
When transmitting HDLC messages, the host can choose to be interrupt driven, or to poll to desired status
registers, or a combination of polling and interrupt processes can be used. An example routine for using the
DS26528 HDLC receiver is given in
FIFO Information
HDLC Transmit Example
Figure
8-10.
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DS26528 Octal T1/E1/J1 Transceiver