DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 217

• Manufacturer Part Number: DS26528GNA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GNA4

• Part # Aliases: 90-26528-NA4

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Per-Channel Loopback Enable for Channels 1 to 32 (CH[1:32]).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Setting any of the CH[1:32] bits in the TBPCS1:TBPCS4 registers will enable the transmit BERT clock for the
associated channel time, and allow mapping of the selected channel data out of the receive BERT port. Multiple or
all channels can be selected simultaneously.
0 = loopback disabled
1 = enable loopback; source data from the corresponding receive channel
(MSB) 7
(MSB)
CH16
CH24
CH32
CH16
CH24
CH32
CH8
CH8
0
0
CH15
CH23
CH31
CH15
CH23
CH31
CH7
CH7
PCL1, PCL2, PCL3, PCL4
Per-Channel Loopback Enable Registers 1 to 4
1D0h, 1D1h, 1D2h, 1D3h + (200h x n): where n = 0 to 7, for Ports 1 to 8
TBPCS1, TBPCS2, TBPCS3, TBPCS4
Transmit BERT Port Channel Select Registers 1 to 4
1D4h, 1D5h, 1D6h, 1D7h + (200h x n): where n = 0 to 7, for Ports 1 to 8
0
6
0
CH14
CH22
CH30
CH14
CH22
CH30
CH6
CH6
0
5
0
CH13
CH21
CH29
CH13
CH21
CH29
CH5
CH5
0
4
0
217 of 276
CH12
CH20
CH28
CH12
CH20
CH28
CH4
CH4
0
3
0
CH11
CH19
CH27
CH11
CH19
CH27
CH3
CH3
0
2
0
DS26528 Octal T1/E1/J1 Transceiver
CH10
CH18
CH26
CH10
CH18
CH26
CH2
CH2
0
1
0
0 (LSB)
(LSB)
CH17
CH25
CH17
CH25
CH1
CH9
CH1
CH9
0
0
PCL1
PCL2
PCL3
PCL4
(E1 Mode
Only)
TBPCS1
TBPCS2
TBPCS3
TBPCS4
(E1 Mode
Only)