DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 275

• Manufacturer Part Number: DS26528GNA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GNA4

• Part # Aliases: 90-26528-NA4

16.
REVISION
072304
120204
012405
081805
071006
102506
DATE
DOCUMENT REVISION HISTORY
New Product Release.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Corrected the Recommended Supply Decoupling Capacitor values: changed the digital
11. Figure 8-1: Added associated port number to each analog ATVDD/ATVSS and
12. Added a note to TTIP and TRING Pin descriptions in Table 8-1 to clarify that the two pins
13. Corrected the AIS (Blue Alarm) set criteria from 5 or less zeros in a 3ms window to 4 or
14. Added E1BCR1 and E1EBCR2 to Table 9-22.
15.
Removed references to RPOS/RNEG, TPOS/TNEG and replaced them with RTIP/RRING
and TTIP/TRING for clarification.
Corrected the typical current draw in Section 12.
Updated ordering information and absolute maximum ratings specs to show DS26528G and
DS26528GN package variants.
Replaced Figure 9-11 with corrected recommended network interface.
Added lead-free package (DS26528GN+) to Ordering Information table.
Removed incorrect reference to JACLK in Section 9.11.3.
Changed IDR register default value for Bit 1 from 0 to 1 (rev A4).
Updated package information drawing and added link to online drawing.
Added commercial range parts to Ordering Information table.
Updated entire data sheet for typos and clarity to match the TEX-family data sheets
(DS26521, DS26522, DS26524).
Modified description of TFPT bit for TCR1 (T1 Mode).
Corrected the default direction of RIOCR.RSIO = 1 to show that the default direction of
RSYNC is Input.
Added Figure 13-3 for BPCLK and TSSYNCIO timing and updated Table 13-3.
Corrected Figure 7-3 to show different relationship of TSSYNCIO depending on the
operation mode (either Input or Output).
Added Section 9.9.6.3 to provide more details on Sa bit support.
Modified RIM7 register at address 0A6h for E1 mode document additional Sa bit support.
Added E1RSAIMR (014h) for E1 mode to allow Sa bit interrupt masks.
Added SABITS (06Eh) register to indicate the last valid Sa bits received.
Added Sa6CODE (06Fh) register to indicate the reported Sa6 received pattern.
Changed the recommended Line Interface Circuit (Figure 9-11) to match the Telecom
App Note 324.
recommended value from 0.1μF to 0.01μF because the 0.01μF value was listed twice.
ARVDD/ARVSS pair to help clarify the recommended decoupling for these pins. Note:
The pin locations did not change, and the functional description did not change, the
numbers 1-8 were only added for clarification purposes.
shown should tied together (for example, pins A1 and A2 for TTIP1).
less zeros and changed the clear criteria from 6 or more zeros in a 3ms window to 5 or
more zeros. This is defined in Table 9-23.
Added note to indicate that Transmit Open Circuit Detect and Short Circuit Detect are not
functional in the CSU modes (T1 LBO 5, 6 and 7). This was added in the bit description
of register LLSR Bit 1 (SCD) and Bit2 (OCD), as well as Section 9.11.2.4.
DESCRIPTION
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DS26528 Octal T1/E1/J1 Transceiver
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