DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 66

• Manufacturer Part Number: DS26528GNA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GNA4

• Part # Aliases: 90-26528-NA4

8.9.16 T1 Programmable In-Band Loop Code Detection
The DS26528 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This
function is available only in T1 mode.
Table 8-31. Registers Related to T1 In-Band Loop Code Detection
Receive In-Band Code Control Register
(T1RIBCC)
Receive Up Code Definition Register 1
(T1RUPCD1)
Receive Up Code Definition Register 2
(T1RUPCD2)
Receive Down Code Definition Register 1
(T1RDNCD1)
Receive Down Code Definition Register 2
(T1RDNCD2)
Receive Spare Code Register 1 (T1RSCD1)
Receive Spare Code Register 2 (T1RSCD2)
Receive Real-Time Status Register 3 (RRTS3)
Receive Latched Status Register 3 (RLS3)
Receive Interrupt Mask Register 3 (RIM3)
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 8 for Framers 2 to 8.
The framer has three programmable pattern detectors. Typically, two of the detectors are used for “loop-up” and
“loop-down” code detection. The user programs the codes to be detected in the Receive Up Code Definition
registers
T1RDNCD2). The length of each pattern is selected via the Receive In-Band Code Control register (T1RIBCC).
There is a third detector (Spare) and it is defined and controlled via the
registers. When detecting a 16-bit pattern, both receive code definition registers are used together to form a 16-bit
register. For 8-bit patterns, both receive code definition registers are filled with the same value. Detection of a 1-,
2-, 3-, 4-, 5-, 6-, and 7-bit pattern only requires the first receive code definition register to be filled. The framer
detects repeating pattern codes in both framed and unframed circumstances with bit-error rates as high as 10E-2.
The detectors can handle both F-bit inserted and F-bit overwrite patterns. Writing the least significant byte of the
receive code definition register resets the integration period for that detector. The code detector has a nominal
integration period of 48ms. Thus, after about 48ms of receiving a valid code, the proper status bit (LUP, LDN, and
LSP) is set to 1. Note that real-time status bits, as well as latched set and clear bits, are available for LUP, LDN,
and LSP
software poll the framer every 50ms to 100ms until 5 seconds has elapsed to ensure that the code is continuously
present.
(T1RUPCD1
(RRTS3
REGISTER
and RLS3). Normally codes are sent for a period of 5 seconds. It is recommended that the
and T1RUPCD2) and the Receive Down Code Definition registers
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ADDRESSES
FRAMER
0ACh
0ADh
0AEh
0AFh
09Ch
09Dh
0B2h
0A2h
082h
092h
Used for selecting length of receive in-
band loop code register.
Receive up code definition register 1.
Receive up code definition register 2.
Receive down code definition register 1.
Receive up code definition register 2.
Receive spare code register 1.
Receive spare code register 2.
Real-time loop code detect.
Latched loop code detect bits.
Mask for latched loop code detect bits.
DS26528 Octal T1/E1/J1 Transceiver
T1RSCD1/T1RSCD2
FUNCTION
(T1RDNCD1
and
T1RSCC
and