DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 183

• Manufacturer Part Number: DS26528GNA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GNA4

• Part # Aliases: 90-26528-NA4

9.4.2 Transmit Register Definitions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Number of Flags Select (NOFS).
Bit 6: Transmit End of Message and Loop (TEOML). To loop on a message, this bit should be set to a one just
before the last data byte of an HDLC packet is written into the transmit FIFO. The message will repeat until the
user clears this bit or a new message is written to the transmit FIFO. If the host clears the bit, the looping message
will complete then flags will be transmitted until new message is written to the FIFO. If the host terminates the loop
by writing a new message to the FIFO the loop will terminate, one or two flags will be transmitted and the new
message will start. If not disabled via TCRCD, the transmitter will automatically append a 2-byte CRC code to the
end of all messages.
Bit 5: Transmit HDLC Reset (THR). Will reset the transmit HDLC controller and flush the transmit FIFO. An abort
followed by 7Eh or FFh flags/idle will be transmitted until a new packet is initiated by writing new data into the
FIFO. This is an acknowledged reset, that is, the host need only to set the bit and the DS26528 will clear it once
the reset operation is complete. Total time for the reset is less than 250μs.
Note: This bit will clear automatically if TMMR.INT_DONE has been set.
Bit 4: Transmit HDLC Mapping Select (THMS).
Bit 3: Transmit Flag/Idle Select (TFS). This bit selects the inter-message fill character after the closing and before
the opening flags (7Eh).
Bit 2: Transmit End of Message (TEOM). Should be set to a one just before the last data byte of an HDLC packet
is written into the transmit FIFO at THF. If not disabled via TCRCD, the transmitter will automatically append a
2-byte CRC code to the end of the message.
Bit 1: Transmit Zero Stuffer Defeat (TZSD). The zero stuffer function automatically inserts a zero in the message
field (between the flags) after five consecutive ones to prevent the emulation of a flag or abort sequence by the
data pattern. The receiver automatically removes (destuffs) any zero after five ones in the message field.
Bit 0: Transmit CRC Defeat (TCRCD). A 2-byte CRC code is automatically appended to the outbound message.
This bit can be used to disable the CRC function.
0 = send one flag between consecutive messages
1 = send two flags between consecutive messages
0 = Normal operation
1 = Reset transmit HDLC controller and flush the transmit FIFO
0 = Transmit HDLC assigned to channels
1 = Transmit HDLC assigned to FDL (T1 mode), Sa bits (E1 mode). This mode must be enabled with
TCR2.7.
0 = 7Eh
1 = FFh
0 = enable the zero stuffer (normal operation)
1 = disable the zero stuffer
0 = enable CRC generation (normal operation)
1 = disable CRC generation
NOFS
7
0
THC1
Transmit HDLC Control Register 1
110h + (200h x n): where n = 0 to 7, for Ports 1 to 8
TEOML
6
0
THR
5
0
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THMS
4
0
TFS
3
0
DS26528 Octal T1/E1/J1 Transceiver
TEOM
2
0
TZSD
1
0
TCRCD
0
0