DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 119

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DS26528GNA4

Manufacturer Part Number
DS26528GNA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS26528GNA4

Part # Aliases
90-26528-NA4
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
The GBISR register reports the interrupt status for each of the eight T1/E1 bit error-rate testers (BERTs). A logic
one in the associated bit location indicates a BERT has set its interrupt signal.
Bit 7: BERT Interrupt Status 8 (BIS8).
Bit 6: BERT Interrupt Status 7 (BIS7).
Bit 5: BERT Interrupt Status 6 (BIS6).
Bit 4: BERT Interrupt Status 5 (BIS5).
Bit 3: BERT Interrupt Status 4 (BIS4).
Bit 2: BERT Interrupt Status 3 (BIS3).
Bit 1: BERT Interrupt Status 2 (BIS2).
Bit 0: BERT Interrupt Status 1 (BIS1).
0 = BERT 8 has not issued an interrupt.
1 = BERT 8 has issued an interrupt.
0 = BERT 7 has not issued an interrupt.
1 = BERT 7 has issued an interrupt.
0 = BERT 6 has not issued an interrupt.
1 = BERT 6 has issued an interrupt.
0 = BERT 5 has not issued an interrupt.
1 = BERT 5 has issued an interrupt.
0 = BERT 4 has not issued an interrupt.
1 = BERT 4 has issued an interrupt.
0 = BERT 3 has not issued an interrupt.
1 = BERT 3 has issued an interrupt.
0 = BERT 2 has not issued an interrupt.
1 = BERT 2 has issued an interrupt.
0 = BERT 1 has not issued an interrupt.
1 = BERT 1 has issued an interrupt.
BIS8
7
0
GBISR
Global BERT Interrupt Status Register
0FAh
BIS7
6
0
BIS6
5
0
119 of 276
BIS5
4
0
BIS4
3
0
DS26528 Octal T1/E1/J1 Transceiver
BIS3
2
0
BIS2
1
0
BIS1
0
0

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