DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 210

• Manufacturer Part Number: DS26528GNA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GNA4

• Part # Aliases: 90-26528-NA4

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Transmit Elastic Store Full Event (TESF).
Bit 6: Transmit Elastic Store Empty Event (TESEM).
Bit 5: Transmit Elastic Store Slip Occurrence Event (TSLIP).
Bit 4: Transmit SLC-96 Multiframe Event (TSLC96) (T1 Mode Only).
Bit 3 (T1 Mode): Transmit Pulse Density Violation Event (TPDV).
Bit 3 (E1 Mode): Transmit Align Frame Event (TAF).
Bit 2: Transmit Multiframe Event (TMF).
Bit 1: Loss of Transmit Clock Clear Condition (LOTCC).
Bit 0: Loss of Transmit Clock Condition (LOTC).
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
TESF
TESF
7
0
TIM1
Transmit Interrupt Mask Register 1
1A0h + (200h x n): where n = 0 to 7, for Ports 1 to 8
TESEM
TESEM
6
0
TSLIP
TSLIP
5
0
TSLC96
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4
0
TPDV
TAF
3
0
DS26528 Octal T1/E1/J1 Transceiver
TMF
TMF
2
0
LOTCC
LOTCC
1
0
LOTC
LOTC
0
0