DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 211

• Manufacturer Part Number: DS26528GNA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GNA4

• Part # Aliases: 90-26528-NA4

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 4: Transmit FDL Register Empty (TFDLE) (T1 Mode Only).
Bit 3: Transmit FIFO Underrun Event (TUDR).
Bit 2: Transmit Message End Event (TMEND).
Bit 1: Transmit FIFO Below Low Watermark Set Condition (TLWMS).
Bit 0: Transmit FIFO Not Full Set Condition (TNFS).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Loss of Frame Synchronization Detect (LOFD).
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
—
—
—
7
0
7
0
TIM2
Transmit Interrupt Mask Register 2 (HDLC)
1A1h + (200h x n): where n = 0 to 7, for Ports 1 to 8
TIM3
Transmit Interrupt Mask Register 3 (Synchronizer)
1A2h + (200h x n): where n = 0 to 7, for Ports 1 to 8
—
—
—
6
0
6
0
—
—
—
5
0
5
0
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TFDLE
—
—
4
0
4
0
TUDR
TUDR
—
3
0
3
0
DS26528 Octal T1/E1/J1 Transceiver
TMEND
TMEND
—
2
0
2
0
TLWMS
TLWMS
—
1
0
1
0
LOFD
TNFS
TNFS
0
0
0
0