DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 49

• Manufacturer Part Number: DS26528GNA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GNA4

• Part # Aliases: 90-26528-NA4

8.9.3 T1 Transmit Synchronizer
The DS26528 transmitter can identify the D4 or ESF frame boundary, as well as the CRC multiframe boundaries
within the incoming NRZ data stream at TSER. The TFM (TCR3.2) control bit determines whether the transmit
synchronizer searches for the D4 or ESF multiframe. Additional control signals for the transmit synchronizer are
located in the
synchronization has occurred. The real-time bit (LOF) is also provided to indicate when the synchronizer is
searching for frame/multiframe alignment. The LOFD bit can be enabled to cause an interrupt condition on INTB.
Note that when the transmit synchronizer is used, the TSYNC signal should be set as an output (TSIO = 1) and the
recovered frame-sync pulse will be output on this signal. The recovered CRC-4 multiframe sync pulse is output if
enabled with TIOCR.0 (TSM = 1).
Other key points concerning the E1 transmit synchronizer:
The Tx synchronizer cannot search for the CAS multiframe.
synchronizer.
Table 8-15. Registers Related to the Transmit Synchronizer
Transmit Synchronizer Control Register
(TSYNCC)
Transmit Control Register 3 (TCR3)
Transmit Latched Status Register 3
(TLS3)
Transmit Interrupt Mask Register 3
(TIM3)
Transmit I/O Configuration Register
(TIOCR)
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 8 for Framers 2 to 8.
1) The Tx synchronizer is not operational when the transmit elastic store is enabled, including IBO modes.
2) The Tx synchronizer does not perform CRC-6 alignment verification (ESF mode) and does not verify
CRC-4 codewords.
TSYNCC
REGISTER
register. The latched status bit TLS3.0 (LOFD) is provided to indicate that a loss-of-frame
ADDRESSES
FRAMER
18Eh
1A2h
183h
192h
184h
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Table 8-15
Resynchronization control for the transmit
synchronizer.
TFM bit selects between D4 and ESF for the
transmit synchronizer.
Provides latched status for the transmit
synchronizer.
Provides mask bits for the TLS3 status.
TSYNC should be set as an output.
shows the registers related to the transmit
DS26528 Octal T1/E1/J1 Transceiver
FUNCTION