DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 151

• Manufacturer Part Number: DS26528GNA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GNA4

• Part # Aliases: 90-26528-NA4

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: One-Second Select (1SECS). This bit allows for synchronization of the error counter updates between
multiple ports. When ERCNT.3 = 0, setting this bit (on a specific framer) will update the framer’s error counters on
the transition of the one-second timer from framer 1. Note that this bit should always be clear for framer 1.
Bit 6: Manual Counter Update Select (MCUS). When manual update mode is enabled with EAMS, this bit can be
used to allow the incoming LATCH_CNT signal to latch all counters. Used for synchronously latching counters or
multiple DS26528 cores located on the same die.
Bit 5: Manual Error Counter Update (MECU). When enabled by ERCNT.3, the changing of this bit from 0 to 1
allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. The
user must wait a minimum of 250μs before reading the error count registers to allow for proper update.
Bit 4: Error Counter Update Select (ECUS).
Bit 3: Error Accumulation Mode Select (EAMS).
Bit 2: PCVCR Fs-Bit Error Report Enable (FSBE) (T1 Mode Only).
Bit 1: Multiframe Out of Sync Count Register Function Select (MOSCRF) (T1 Mode Only).
Bit 0: T1 Line Code Violation Count Register Function Select (LCVCRF).
0 = use the one-second timer that is internal to the framer
1 = use the one-second timer from framer 1 to latch updates
0 = MECU is used to manually latch counters
1 = counters are latched on the rising edge of the LATCH_CNT signal
T1 Mode:
0 = update error counters once a second
1 = update error counters every 42ms (333 frames)
E1 Mode:
0 = update error counters once a second
1 = update error counters every 62.5ms (500 frames)
0 = automatic updating of error counters enabled. The state of ERCNT.4 determines accumulation time
(timed update)
1 = user toggling of ERCNT.5 determines accumulation time (manual update)
0 = do not report bit errors in Fs-bit position; only Ft-bit position
1 = report bit errors in Fs-bit position as well as Ft-bit position
0 = count errors in the framing bit position
1 = count the number of multiframes out of sync
0 = do not count excessive zeros
1 = count excessive zeros
1SECS
1SECS
7
0
ERCNT
Error-Counter Configuration Register
086h + (200h x n): where n = 0 to 7, for Ports 1 to 8
MCUS
MCUS
6
0
MECU
MECU
5
0
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ECUS
ECUS
4
0
EAMS
EAMS
3
0
DS26528 Octal T1/E1/J1 Transceiver
FSBE
—
2
0
MOSCRF
—
1
0
LCVCRF
LCVCRF
0
0