DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 170

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DS26528GNA4

Manufacturer Part Number
DS26528GNA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS26528GNA4

Part # Aliases
90-26528-NA4
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Receive Elastic Store Full Event (RESF).
Bit 6: Receive Elastic Store Empty Event (RESEM).
Bit 5: Receive Elastic Store Slip Occurrence Event (RSLIP).
Bit 3: Receive-Signaling Change-of-State Event (RSCOS).
Bit 2: One-Second Timer (1SEC).
Bit 1: Timer Event (TIMER).
Bit 0: Receive Multiframe Event (RMF).
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
RESF
7
0
RIM4
Receive Interrupt Mask Register 4
0A3h + (200h x n): where n = 0 to 7, for Ports 1 to 8
RESEM
6
0
RSLIP
5
0
170 of 276
4
0
RSCOS
3
0
DS26528 Octal T1/E1/J1 Transceiver
1SEC
2
0
TIMER
1
0
RMF
0
0

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