DS26528-W Maxim Integrated Products, DS26528-W Datasheet
DS26528-W
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DS26528-W Summary of contents
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... GENERAL DESCRIPTION The DS26528 is a single-chip 8-port framer and line interface unit (LIU) combination for T1, E1, and J1 applications. Each channel configurable, supporting both long-haul and short-haul lines. APPLICATIONS Routers Channel Service Units (CSUs) Data Service Units (DSUs) Muxes Switches Channel Banks ...
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... Signaling .............................................................................................................................................. 50 8.9.5 T1 Data Link......................................................................................................................................... 54 8.9.6 E1 Data Link......................................................................................................................................... 56 8.9.7 Maintenance and Alarms ..................................................................................................................... 57 8.9.8 E1 Automatic Alarm Generation .......................................................................................................... 60 8.9.9 Error-Count Registers .......................................................................................................................... 61 8.9.10 DS0 Monitoring Function...................................................................................................................... 63 8.9.11 Transmit Per-Channel Idle Code Insertion........................................................................................... 64 TABLE OF CONTENTS .............................................................................................................9 ................................................................................................................12 ......................................................................................................19 ................................................................................................................27 M ..............................................................................................29 OWN ODES ..............................................................................................30 ................................................................................................................30 ................................................................................................... 276 DS26528 Octal T1/E1/J1 Transceiver ...
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... S (BERT) F ................................................................................86 UNCTION ..................................................................................................109 .................................................................................................124 .........................................................................................................218 .....................................................................................................227 T D ..........................................................................235 IMING IAGRAMS T D ....................................................................240 IMING IAGRAMS T D ..........................................................................245 IMING IAGRAMS T D ....................................................................247 IMING IAGRAMS ....................................................................................................251 ..........................................................................................251 AC C ........................................................................252 US HARACTERISTICS .........................................................................................................261 ....................................................................................262 HARACTERISTICS M .........................................................................................264 TATE ACHINE 3 of 276 DS26528 Octal T1/E1/J1 Transceiver ...
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... ODES 13 .....................................................................................................................268 EST EGISTERS 13.4.1 Boundary Scan Register .................................................................................................................... 268 13.4.2 Bypass Register ................................................................................................................................. 268 13.4.3 Identification Register......................................................................................................................... 268 14. PIN CONFIGURATION...................................................................................................273 15. PACKAGE INFORMATION ............................................................................................274 15.1 256-B TE-CSBGA (56-G6028-001) ...................................................................................274 ALL 16. DOCUMENT REVISION HISTORY ................................................................................275 ...........................................................................................................267 4 of 276 DS26528 Octal T1/E1/J1 Transceiver ...
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... Figure 8-16. Analog Loopback................................................................................................................................... 84 Figure 8-17. Local Loopback ..................................................................................................................................... 84 Figure 8-18. Remote Loopback ................................................................................................................................. 85 Figure 8-19. Dual Loopback ...................................................................................................................................... 85 Figure 9-1. Register Memory Map for the DS26528.................................................................................................. 89 Figure 10-1. T1 Receive-Side D4 Timing ................................................................................................................ 235 Figure 10-2. T1 Receive-Side ESF Timing.............................................................................................................. 235 Figure 10-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................... 236 Figure 10-4 ...
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... Figure 12-11. Transmit Formatter Timing—Line Side ............................................................................................. 260 Figure 12-12. JTAG Interface Timing Diagram........................................................................................................ 261 Figure 13-1. JTAG Functional Block Diagram ......................................................................................................... 263 Figure 13-2. TAP Controller State Diagram............................................................................................................. 266 Figure 14-1. Pin Configuration—256-Ball TE-CSBGA ............................................................................................ 273 DS26528 Octal T1/E1/J1 Transceiver 6 of 276 ...
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... Table 8-32. Registers Related to Framer Payload Loopbacks.................................................................................. 67 Table 8-33. Registers Related to the HDLC .............................................................................................................. 68 Table 8-34. Recommended Supply Decoupling ........................................................................................................ 75 Table 8-35. Registers Related to Control of DS26528 LIU ....................................................................................... 76 Table 8-36. Telecommunications Specification Compliance for DS26528 Transmitters .......................................... 77 Table 8-37. Transformer Specifications..................................................................................................................... 77 Table 8-38. ANSI T1.231, ITU-T G.775, and ETS 300 233 Loss Criteria Specifications .......................................... 81 Table 8-39 ...
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... Table 12-3. Transmit AC Characteristics................................................................................................................. 258 Table 12-4. JTAG Interface Timing.......................................................................................................................... 261 Table 12-5. System Clock AC Charateristics .......................................................................................................... 262 Table 13-1. Instruction Codes for IEEE 1149.1 Architecture................................................................................... 267 Table 13-2. ID Code Structure................................................................................................................................. 268 Table 13-3. Boundary Scan Control Bits ................................................................................................................. 268 DS26528 Octal T1/E1/J1 Transceiver 8 of 276 ...
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... Major Operating Modes The DS26528 has two major modes of operation: T1 mode and E1 mode. The mode of operation for the LIU is configured in the LIU Transmit Receive Control register (LTRCR). The mode of operation for the framer is configured in the Transmit Master Mode register (TMMR). J1 operation is a special case of T1 operating mode. ...
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... Full receive and transmit path transparency T1 framing formats D4 and ESF per T1.403, and expanded SLC-96 support (TR-TSY-008) E1 FAS framing and CRC-4 multiframe per G.704, G.706, and G.732 CAS multiframe Transmit-side synchronizer Transmit midpath CRC recalculate (E1) DS26528 Octal T1/E1/J1 Transceiver 10 of 276 ...
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... Hardware signaling capability Receive-signaling reinsertion to a backplane multiframe sync Availability of signaling in a separate PCM data stream Signaling freezing Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode User-selectable synthesized clock output DS26528 Octal T1/E1/J1 Transceiver 11 of 276 ...
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... Loopbacks (remote, local, analog, and per-channel loopback) 2.9 Control Port 8-bit parallel control port Intel or Motorola nonmultiplexed support Flexible status registers support polled, interrupt, or hybrid program environments Software reset supported Hardware reset pin Software access to device ID and silicon revision DS26528 Octal T1/E1/J1 Transceiver 12 of 276 ...
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... APPLICATIONS The DS26528 is useful in applications such as: Routers Channel Service Units (CSUs) Data Service Units (DSUs) Muxes Switches Channel Banks T1/E1 Test Equipment DS26528 Octal T1/E1/J1 Transceiver 13 of 276 ...
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... AIS generation as unframed all ones is defined. The total cable attenuation is defined as 22dB. The DS26528 functions with up to -36dB cable loss. Note that the pulse template defined by T1.403 and T1.102 are different, specifically at Times 0.61, -0.27, -34, and 0.77. The DS26528 is compliant to both templates. ...
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... Jitter transfer between 2.048 synchronization signal and 2.048 transmission signal is provided. ITU-T G.742 Second-Order Digital Multiplex Equipment Operating at 8448kbps The DS26528 jitter attenuator is complaint with jitter transfer curve for sinusoidal jitter input. ITU-T G.772 This specification provides the method for using receiver for transceiver monitor for the remaining seven transmitter/receiver combinations ...
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... Locked refers to two clock signals that are phase- or frequency-locked or derived from a common clock (i.e., a 1.544MHz clock can be locked to a 2.048MHz clock if they share the same 8kHz component). Table 5-1. Time Slot Numbering Schemes Channel Phone Channel 276 DS26528 Octal T1/E1/J1 Transceiver ...
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... CONTROLLER PORT LIU #8 FRAMER #8 FRAMER #7 FRAMER #6 FRAMER #5 FRAMER #4 FRAMER #3 FRAMER #2 T1/E1 FRAMER HDLC BERT JTAG PORT TEST PORT 17 of 276 DS26528 Octal T1/E1/J1 Transceiver INTERFACE #8 INTERFACE #7 INTERFACE #6 INTERFACE #5 INTERFACE #4 RECEIVE INTERFACE #3 BACKPLANE INTERFACE #2 SIGNALS BACKPLANE TRANSMIT BACKPLANE INTERFACE SIGNALS ELASTIC STORES ...
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... Tx FRAMER: B8ZS/ HDB3 ELASTIC ENCODE STORE Rx FRAMER: B8ZS/ HDB3 ELASTIC DECODE STORE Rx BERT JTAG RESET PORT BLOCK 18 of 276 DS26528 Octal T1/E1/J1 Transceiver Tx HDLC Tx SIGNALING/ CHANNEL BLOCKING TCLKn TSERn TSYNCn TSSYNCIO (INPUT MODE) TSYSCLK RSYSCLK RSYNCn RSERn RCLKn Rx SIGNALING/ Rx CHANNEL BLOCKING ...
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... Receive Bipolar Ring for Transceiver The differential inputs of RTIPn and RRINGn can provide internal matched impedance for E1 75Ω, E1 120Ω, T1 100Ω 110Ω. The user has the option of turning off internal termination via the LIU Receive Impedance and Sensitivity Monitor register (LRISMR 276 DS26528 Octal T1/E1/J1 Transceiver FUNCTION ...
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... BPCLK will be generated. This pulse in combination with BPCLK can be used as an IBO master. The BPCLK can be sourced to RSYSCLK, TSYSCLK, and TSSYNCIO as a source to RSYNC, and TSSYNCIO of DS26528 or RSYNC and TSSYNC of other Dallas Semiconductor parts. Transmit Signaling. When enabled, this input samples signaling bits for insertion into outgoing PCM data stream ...
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... RSYNC can be programmed to output double-wide pulses on signaling frames in T1 mode mode, RSYNC out can be used to indicate CAS and CRC-4 multiframe. The DS26528 can accept H.100-compatible synchronization signal. The default direction of this pin at power-up is input, as determined by the RSIO control bit in the RIOCR.2 register. ...
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... Transceiver Clock Control register (GTCCR If framer LOS is selected, this pin can be programmed to toggle high when the framer detects an LOS condition, or when the signaling data is frozen via either automatic or manual intervention. The indication is used to alert downstream equipment of the condition 276 DS26528 Octal T1/E1/J1 Transceiver ). ...
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... The reference for this clock can be RCLK from any of the LIU, 1.544MHz, or 2.048MHz frequency derived from MCLK or an external reference clock. This allows for the IBO clock to reference from external source or T1J1E1 recovered clock or the MCLK oscillator 276 DS26528 Octal T1/E1/J1 Transceiver ...
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... RDB and CSB are low. Write-Read Bar/Read-Write Bar. This active-low signal along with CSB qualifies write access to one of the DS26528 registers. Data at D[7:0] is written into the addressed register at the rising edge of WRB while CSB is low. ...
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... Output: This signal can also be used to output a 1.544MHz or 2.048MHz reference clock. This allows for multiple DS26528s to share the same reference for generation of the backplane clock. Hence system consisting of multiple DS26528s, one can be a master and others a slave using the same reference clock. TEST Digital Enable ...
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... J5, J6, DVSSIO — J10, J11 FUNCTION POWER SUPPLIES 3.3V Analog Transmit Power Supply. These V LIU sections of the DS26528. Analog Transmit V . These pins are used for transmit analog V SS 3.3V Analog Receive Power Supply. These V LIU sections of the DS26528. Analog Receive V . These pins are used for analog V ...
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... This backplane clock and frame pulse (TSSYNCIO) can be used by the DS26528 and other IBO-equipped devices as an IBO bus master. Hence, the DS26528 provides the 8kHz sync pulse and 4MHz, 8MHz, and 16MHz clock. This can be used by the link layer devices and frames connected to the IBO bus. ...
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... If MCLK or RCLK is used as a reference, REFCLKIO can be used to provide a 2.048MHz or 1.544MHz clock for external use. BPREFSEL3:0 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8 MCLKT1 MCLKE1 REFCLKIO 28 of 276 DS26528 Octal T1/E1/J1 Transceiver BPCLK1:0 BFREQSEL BPCLK CLK GEN REFCLKIO TSSYNCIO ...
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... This includes writing reserved locations to 00h. The DS26528 has several features included to reduce power consumption. The LIU transmitters can be powered down by setting the TPDE bit in the LIU Maintenance Control register (LMCR). Note that powering down the transmit LIU results in a high-impedance state for the corresponding TTIP and TRING pins and reduced operating current ...
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... E1TNAF registers as required. Configure the framer Transmit TMMR and RMMR registers for each framer. GBISR to identify which of the eight transceivers is causing the 30 of 276 DS26528 Octal T1/E1/J1 Transceiver TMMR and RMMR registers. If using software transmit (RCR1 (T1)/RCR1 LTRCR TIIR or RIIR ...
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... BERT Bit Counter Overflow BERT Error Counter Overflow BERT Receive All Ones BERT Receive All Zeros BERT Receive Loss of Synchronization BERT in Synchronization INTERRUPT 2 STATUS 1 REGISTERS INTERRUPT MASK REGISTERS — 1 — 276 DS26528 Octal T1/E1/J1 Transceiver DRAWING LEGEND: REGISTER NAME REGISTER NAME ...
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... The elastic stores have two main purposes. First, they can be used for rate conversion. When the DS26528 is in the T1 mode, the elastic stores can rate convert the T1 data stream to a 2.048MHz backplane mode the elastic store can rate convert the E1 data stream ...
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... N bytes < Delay < 1 Frame + N bytes TESCR.2 N bytes < Delay < 1 Frame + N bytes RESCR.3 1/2 Frame < Delay < 1 1/2 Frames TESCR.3 1/2 Frame < Delay < 1 1/2 Frames for higher rate system-clock applications. The user has the option of either 33 of 276 DS26528 Octal T1/E1/J1 Transceiver DELAY ...
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... E1 data for that channel. Typically the user will want to program eight channels to be blanked. The default (power-up) configuration blanks channels 25 to 32, so that the first 24 E1 channels are mapped from the 24 channels of the 1.544MHz backplane. DS26528 Octal T1/E1/J1 Transceiver 34 of 276 ...
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... IBO would have the channel blocks (if programmed active at the rate of 4.096MHz). The particular blocking channel would be active for a duration of the channel if programmed. The DS26528 also supports the traditional mode of IBO operation by allowing complete access to individual framers, and tri-stating the RSER and RSIG pins at the appropriate times for external bus wiring. This mode of operation is enabled per framer in the associated disabled (IBOMS0 = 0 and IBOMS1 = 0) ...
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... RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK 36 of 276 DS26528 Octal T1/E1/J1 Transceiver RSER1 RSIG1 RSYNC1 RSYSCLK TSER1 TSIG1 TSSYNCIO TSYSCLK RSER3 RSIG3 RSYNC3 RSYSCLK TSER3 TSIG3 TSSYNCIO TSYSCLK RSER5 RSIG5 ...
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... TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK 37 of 276 DS26528 Octal T1/E1/J1 Transceiver RSER1 RSIG1 RSYNC1 RSYSCLK TSER1 TSIG1 TSSYNCIO TSYSCLK RSER5 RSIG5 RSYNC5 RSYSCLK TSER5 TSIG5 TSSYNCIO TSYSCLK ...
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... RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG To Mux To Mux RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG To Mux To Mux RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK 38 of 276 DS26528 Octal T1/E1/J1 Transceiver RSER1 RSIG1 RSYNC1 RSYSCLK TSER1 TSIG1 TSSYNCIO TSYSCLK ...
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... Combined Receive Signaling Data for Signaling Data for Ports 5 and 6 Ports 5–8 Unused Combined Receive Signaling Data for Ports 7 and 8 Unused 39 of 276 DS26528 Octal T1/E1/J1 Transceiver 16.384MHz IBO Receive Serial Data for Ports 1–8 Unused Unused Unused Unused Unused Unused Unused 5– ...
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... Signaling Data for Ports 5 and 6 Ports 5–8 Unused Unused Combined Transmit Signaling Data for Unused Ports 7 and 8 Unused Unused 40 of 276 DS26528 Octal T1/E1/J1 Transceiver 16.384MHz IBO Transmit Serial Data for Ports 1–8 1–4 Unused Unused Unused Unused Unused Unused Unused 16 ...
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... Receive Frame Pulse for Ports 5 and 6 for Ports 5–8 Unused Unused Receive Frame Pulse Unused for Ports 7 and 8 Unused Unused 41 of 276 DS26528 Octal T1/E1/J1 Transceiver 16.384MHz IBO Receive Frame Pulse for Ports 1–8 Unused Unused Unused Unused Unused Unused Unused ...
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... The H.100 (or CT bus synchronous, bit-serial, TDM transport bus operating at 8.192MHz. The H.100 standard also allows compatibility modes to operate at 2.048MHz, 4.096MHz, or 8.192MHz. The control bit H100EN (RIOCR.5), when combined with RSYNCINV and TSSYNCINV, allows the DS26528 to accept a CT bus- compatible frame-sync signal (CT_FRAME) at the RSYNC and TSSYNCIO (input mode) inputs. ...
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... T1-to-E1 rate conversion. See Section 8.8.1. 8.8.5 Transmit Fractional Support (Gapped Clock Mode) The DS26528 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN-PRI applications. When the gapped clock feature is enabled, a gated clock is output on the TCHCLK signal ...
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... Framers The DS26528 framer cores are software selectable for T1, J1, or E1. The receive framer locates the frame and multiframe boundaries and monitors the data stream for alarms also used for extracting and inserting signaling data, T1 FDL data, and E1 Si- and Sa-bit information. The receive-side framer decodes AMI, B8ZS line coding, synchronizes to the data stream, reports alarm information, counts framing/coding and CRC errors, and provides clock/data and frame-sync signals to the backplane interface section ...
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... Table 8-11. ESF Framing Mode FRAME FRAMING NUMBER Table 8-12. SLC-96 Framing FRAME NUMBER FDL CRC √ CRC-1 √ √ CRC-2 √ √ CRC-3 √ √ CRC-4 √ √ CRC-5 √ √ CRC-6 √ 276 DS26528 Octal T1/E1/J1 Transceiver SIGNALING √ √ √ √ SIGNALING ...
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... C9 (Concentrator Bit) 1 C10 (Concentrator Bit) 0 C11 (Concentrator Bit (Spoiler Bit (Spoiler Bit (Spoiler Bit (Maintenance Bit (Maintenance Bit (Maintenance Bit (Alarm Bit (Alarm Bit (Switch Bit (Switch Bit (Switch Bit (Switch Bit (Spoiler Bit 276 DS26528 Octal T1/E1/J1 Transceiver SIGNALING ...
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... Table 8-13 Sa4 Sa4 Sa4 Sa4 Sa4 Sa4 Sa4 Sa4 47 of 276 DS26528 Octal T1/E1/J1 Transceiver Sa5 Sa6 Sa7 Sa5 Sa6 Sa7 Sa5 Sa6 Sa7 Sa5 Sa6 Sa7 Sa5 Sa6 Sa7 Sa5 Sa6 Sa7 Sa5 Sa6 Sa7 Sa5 Sa6 Sa7 8 1 Sa8 ...
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... Receive SLC-96 Data Link Register 2 (T1RSLC2) Receive SLC-96 Data Link Register 3 (T1RSLC3) Note: The addresses shown are for Framer 1. Addresses for Framers can be calculated using the following: Framer n = (Framer 1 address + ( 200h); where for Framers DS26528 Octal T1/E1/J1 Transceiver FRAMER ADDRESSES 180h T1/E1 mode. 181h Source of the F-bit ...
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... T1 Transmit Synchronizer The DS26528 transmitter can identify the D4 or ESF frame boundary, as well as the CRC multiframe boundaries within the incoming NRZ data stream at TSER. The TFM (TCR3.2) control bit determines whether the transmit synchronizer searches for the D4 or ESF multiframe. Additional control signals for the transmit synchronizer are ...
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... The DS26528 supports both software- and hardware-based signaling. Interrupts can be generated on changes of signaling data. The DS26528 is also equipped with receive-signaling freeze on loss of synchronization (OOF), carrier loss, or change of frame alignment. The DS26528 also has hardware pins to indicate signaling freeze. • Flexible signaling support ...
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... TSER pin. The user can control which channels are to have signaling data from the TSIG pin inserted into them on a per-channel basis. The signaling insertion capabilities of the framer are available whether the transmit-side elastic store is enabled or disabled. If the elastic store is enabled, the backplane clock (TSYSCLK) can be either 1.544MHz or 2.048MHz 276 DS26528 Octal T1/E1/J1 Transceiver ...
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... Change of State To avoid constant monitoring of the receive-signaling registers, the DS26528 can be programmed to alert the host when any specific channel or channels undergo a change of their signaling state. select which channels can cause a change-of-state indication. The change of state is indicated in Latched Status Register 4 (RLS4 ...
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... TCR3.2 (TFM • TCR1.6 (TFPT The DS26528 automatically inserts the 12-bit alignment pattern in the Fs bits for the SLC-96 data link frame. Data from T1TSLC1:T1TSLC3 is inserted into the remaining Fs-bit locations of the SLC-96 multiframe. The status bit TSLC96 located at TLS1.4 is set to indicate that the SLC-96 data link buffer has been transmitted and that the user should write new message data into T1TSLC1:T1TSLC3 ...
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... SLC-96 alignment pattern. 8.9.5 T1 Data Link 8.9.5.1 T1 Transmit Bit-Oriented Code (BOC) Transmit Controller The DS26528 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. Table 8-18. Registers Related to T1 Transmit BOC ...
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... Receive Bit-Oriented Code (BOC) Controller The DS26528 framers contain a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1, ESF mode in the data link bits. receive BOC operation. Table 8-19. Registers Related to T1 Receive BOC ...
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... T1 data stream. The LSB is transmitted first mode, only the lower six bits are used. 8.9.5.4 Legacy T1 Receive FDL It is recommended that the DS26528’s built-in BOC or HDLC controllers be used for most applications requiring access to the FDL. Table 8-21 shows the registers related to the receive FDL ...
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... Additional E1 Receive Sa- and Si-Bit Receive Operation (E1 Mode) The DS26528, when operated in the E1 mode, provides for access to both the Sa and the Si bits via two methods. The first involves using the internal an expanded version of the first method. 8.9.6.1.1 Internal Register Scheme Based on Double-Frame (Method 1) ...
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... E-Bit Count Register 1 (E1EBCR1) E-Bit Count Register 2 (E1EBCR2) Note: The addresses shown are for Framer 1. Addresses for Framers can be calculated using the following: Framer n = (Framer 1 address + ( 200h); where for Framers DS26528 Octal T1/E1/J1 Transceiver FRAMER ADDRESSES 0B0h Real-time receive status 1. ...
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... RRTS1.0). Latched indication that the receiver has reacquired synchronization since the bit was last cleared. Bit clears when written by the user, even if the condition is still present (falling edge detect of RRTS1.0 276 DS26528 Octal T1/E1/J1 Transceiver ...
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... The definition of the Alarm Indication Signal (Blue Alarm unframed all-ones signal. AIS detectors should be able to operate properly in the presence of a 10E-3 error rate and they should not falsely trigger on a framed all-ones signal. The AIS alarm criteria in the DS26528 has been set to achieve this performance recommended that the RAIS bit be qualified with the RLOF bit. Note 2: ...
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... If a bit is set replacement occurs. 8.9.9 Error-Count Registers The DS26528 contains four counters that are used to accumulate line coding errors, path errors, and synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62.5ms (E1 mode only), or manually. See the Error-Counter Configuration register (ERCNT). When updated automatically, the user can use the interrupt from the timer to determine when to read these registers ...
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... Yes Errors in both the Ft and Fs patterns Errors in the CRC-6 codewords (ERCNT.1) MOS F-Bit MOS F-Bit 62 of 276 DS26528 Octal T1/E1/J1 Transceiver Table 8-27 for a detailed description of PCVCR2 WHAT IS COUNTED IN FOSCR1, FOSCR2 Number of multiframes out of sync Errors in the Ft pattern Number of multiframes out of sync ...
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... The counter is disabled during loss of sync at either the FAS or CRC-4 level; it continues to count if loss of multiframe sync occurs at the CAS level. 8.9.10 DS0 Monitoring Function The DS26528 can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. Table 8-29 Table 8-29 ...
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... E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only) The DS26528 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSER will already have the FAS/NFAS, CRC multiframe alignment word, and CRC-4 checksum in time slot 0. The user can modify the Sa-bit positions and this change in data content will be used to modify the CRC-4 checksum ...
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... T1 Programmable In-Band Loop Code Generator The DS26528 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. Table 8-30. Registers Related to T1 In-Band Loop Code Generator REGISTER Transmit Code Definition Register 1 ...
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... T1 Programmable In-Band Loop Code Detection The DS26528 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. Table 8-31. Registers Related to T1 In-Band Loop Code Detection REGISTER Receive In-Band Code Control Register ...
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... Note: The addresses shown are for Framer 1. Addresses for Framers can be calculated using the following: Framer n = (Framer 1 address + ( 200h); where for Framers 083h Transmit data output from the framer is looped back to the receiver. 083h The 192-bit payload data is looped back to the transmitter. 083h Data recovered by the receiver is looped back to the transmitter 276 DS26528 Octal T1/E1/J1 Transceiver FUNCTION ...
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... HDLC Controllers 8.10.1 Receive HDLC Controller The DS26528 has an enhanced HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). The HDLC controller has a 64-byte FIFO buffer in both the transmit and receive paths. The user can select any specific bits within the time slot(s) to assign to the HDLC controller, as well as specific Sa bits (E1 mode) ...
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... The HDLC status registers in the DS26528 allow for flexible software interface to meet the user’s preferences. When receiving HDLC messages, the host can choose to be interrupt driven poll to desired status registers combination of polling and interrupt processes can be used. An example routine for using the DS26528 HDLC receiver is given in Figure 8-9 ...
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... Interrupt? YES Read Register RHPBA YES (MS = RHPBA[7]) Read N Bytes From Read N Bytes From Rx HDLC FIFO (RHF) Rx HDLC FIFO (RHF RHPBA[5.. RHPBA[5..0] Read RRTS5 for Packet Status (PS2..0) Take appropriate action 70 of 276 DS26528 Octal T1/E1/J1 Transceiver No Action Required Work Another Process. ...
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... HDLC Transmit Example The HDLC status registers in the DS26528 allow for flexible software interface to meet the user’s preferences. When transmitting HDLC messages, the host can choose to be interrupt driven poll to desired status registers combination of polling and interrupt processes can be used. An example routine for using the ...
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... Tx HDLC FIFO (THF) Last Byte of YES Message TLWM A Interrupt? YES NO Disable TMEND Interrupt Prepare New Message 72 of 276 DS26528 Octal T1/E1/J1 Transceiver Set TEOM (THC1.2) Push Last Byte into Tx FIFO Enable TMEND Interrupt NO TMEND A Interrupt? YES Read TUDR Status Bit TUDR = 1 YES ...
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... Line Interface Units (LIUs) The DS26528 has eight identical LIU transmit and receive front-ends for the eight framers. Each LIU contains three sections: the transmitter, which waveshapes and drives the network line; the receiver, which handles clock and data recovery; and the jitter attenuator. The DS26528 LIUs can switch between networks without changing any external components on either the transmit or receive side. circuit for software-selected termination with protection. In this configuration, the device can connect to 100Ω ...
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... T4 S2 1:1 60 0.1 uF DESCRIPTION SMP 1.25 F1250T P0080SA MC P1800SC MC P0300SC MC PE-68678 PE-65857 or in Application Note 324, which is available at www.maxim-ic.com/AN324 276 DS26528 Octal T1/E1/J1 Transceiver DVDD TTIP 0.01 uF DVSS TRING Dallas Single Chip Transceiver or Line Interface Unit TVDD RTIP 0.1 uF TVSS RVDD ...
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... ARVDD/ARVSS pair (8 total), one 1μF for every two ARVDD/ARVSS pairs (4 total), and two 10μF capacitors for the analog receive supply pins. These capacitors should be located as close to the intended power pins as possible. — 0.1μF + 1μF + 10μ 276 DS26528 Octal T1/E1/J1 Transceiver NOTES ...
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... Data input to the transmit side of the LIU is sent via the jitter attenuation mux to the waveshaping circuitry and line driver. The DS26528 drives the line from the TTIP and TRING pins via a coupling transformer. The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or short-haul (DSX-1) lines for T1 ...
Page 77
... T1/J1 operation. The DS26528 drivers have a short-circuit and open-circuit detection driver-fail monitor. The TXENABLE pin can high impedance the transmitter outputs for protection switching. The individual transmitters can also be placed in high impedance through register settings. The DS26528 also has functionality for powering down the transmitters individually ...
Page 78
... Transmit-Line Pulse Shapes The DS26528 transmitters can be selected individually to meet the pulse templates for E1 and T1/J1 modes. The T1/J1 pulse template is shown in shape can be configured for each LIU on an individual basis. The LIU transmit impedance selection registers can be used to select an internal transmit terminating impedance of 100Ω for T1, 110Ω for J1 mode, 75Ω or 120Ω for E1 mode or no internal termination for mode ...
Page 79
... Transmit Open-Circuit Detector The DS26528 can also detect when the TTIP or TRING outputs are open circuited. OCS (LRSR.1) provides a real- time indication of when an open circuit is detected. Register which can be used to activate an interrupt when enabled via the not available in T1 CSU operating modes (LBO5, LBO6, and LBO7) ...
Page 80
... Receive sensitivity is configurable by setting the appropriate RSMS[1:0] bits (LRISMR). The DS26528 uses a digital clock recovery system. The resultant E1, T1 clock derived from MCLK is multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16 times oversampler, which is used to recover the clock and data ...
Page 81
... Loss of Signal (LOS) The DS26528 uses both the digital and analog loss-detection method in compliance with the latest ANSI T1.231 for T1/J1 and ITU-T G.775, or ETS 300 233 for E1 mode of operation. Loss of signal (LOS) is detected if the receiver level falls below a threshold analog voltage for certain duration. ...
Page 82
... For long-haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based on Table 9-19) continuous duration of 2048-bit periods (1ms). LOS is reset if the receive signal level is greater than or equal to the programmed sensitivity level for a duration of 192-bit periods. DS26528 Octal T1/E1/J1 Transceiver 82 of 276 ...
Page 83
... Jitter Attenuator The DS26528 contains a jitter attenuator for each LIU that can be set to a depth 128 bits via the JADS (LTRCR.4) bit in the LIU Transmit Receive Control register (LTRCR). The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay-sensitive applications ...
Page 84
... LIU Loopbacks The DS26528 provides four LIU loopbacks for diagnostic purposes: analog loopback, local loopback, remote loopback, and dual loopback. In the loopback diagrams that follow, TSER, TCLK, RSER, and RCLK are inputs/outputs from the framer. Note that the framer input/output can be in IBO mode where a single TSER/RSER can be shared eight framers ...
Page 85
... RECEIVE RECEIVE DIGITAL ANALOG JITTER RECEIVE RECEIVE DIGITAL ANALOG TRANSMIT TRANSMIT DIGITAL ANALOG RECEIVE RECEIVE DIGITAL ANALOG 85 of 276 DS26528 Octal T1/E1/J1 Transceiver Figure 8-18. TTIP TTIP LINE LINE DRIVER DRIVER TRING TRING RTIP RTIP RRING RRING Figure 8-19. TTIP LINE ...
Page 86
... BERT Status Interrupt Mask Register (BSIM) Note: The addresses shown are for Framer 1.Addresses for Framers can be calculated using the following framer: Framer n = (Framer 1 address + ( 200h); where for Framers DS26528 Octal T1/E1/J1 Transceiver FRAMER ADDRESSES When any of the 8 BERTs issue an interrupt, a 0FAh bit is set ...
Page 87
... BLSR register. TXPC and and RBCS1:RBCS4 registers. Individual bit positions within the channels can be RBPBS registers. Using combinations of these functions, the BERT pattern can 87 of 276 DS26528 Octal T1/E1/J1 Transceiver RXPC registers for each port. The BERT can ...
Page 88
... Dallas Semiconductor octal framer product, DS26401, as well as the DS26521, DS26522, and DS26524. The registers control functions of the framers, LIU, and BERT within the DS26528. The map is divided into eight framers, followed by eight LIUs and eight BERTs. Global registers (applicable to all eight transceivers and BERTs) are located within the address space of Framer 1 ...
Page 89
... Figure 9-1. Register Memory Map for the DS26528 Adrs = 0000 0000 0000 Adrs = 0000 1111 0000 Adrs = 0001 0000 0000 Adrs = 0001 1111 0000 Adrs = 0010 0000 0000 Adrs = 0100 0000 0000 Adrs = 0101 1111 1111 Adrs = 0110 0000 0000 Adrs = 0111 1111 1111 ...
Page 90
... Global Framer Interrupt Status Register Global BERT Interrupt Status Register Global LIU Interrupt Status Register Global Framer Interrupt Mask Register Global BERT Interrupt Mask Register Global LIU Interrupt Mask Register Reserved 90 of 276 DS26528 Octal T1/E1/J1 Transceiver R/W R/W R/W R/W R/W — R/W R/W — ...
Page 91
... Framer Register List Table 9-3. Framer Register List Note: Only the Framer 1 address is presented here.The same set of register definitions applies for Transceiver accordance with the DS26528 map offsets. Transceiver offset 200 hex, where n designates the transceiver in question. ADDRESS NAME 000h–00Fh — ...
Page 92
... E1 Receive SaX Bits Register Received Sa6 Codeword Register Reserved Receive Master Mode Register Receive Control Register 1 (T1 Mode) Receive Control Register 1 (E1 Mode) Receive In-Band Code Control Register (T1 Mode) Receive Control Register 2 (E1 Mode 276 DS26528 Octal T1/E1/J1 Transceiver R/W — ...
Page 93
... Receive Real-Time Status Register 3 (T1 Mode) Receive Real-Time Status Register 3 (E1 Mode) Reserved Receive Real-Time Status Register 5 (HDLC) Receive HDLC Packet Bytes Available Register Receive HDLC FIFO Register 93 of 276 DS26528 Octal T1/E1/J1 Transceiver R/W R/W R/W R/W R/W R/W R/W ...
Page 94
... Transmit Idle Code Definition Register 6 Transmit Idle Code Definition Register 7 Transmit Idle Code Definition Register 8 Transmit Idle Code Definition Register 9 Transmit Idle Code Definition Register 10 Transmit Idle Code Definition Register 276 DS26528 Octal T1/E1/J1 Transceiver 9-2. Note that this space is R/W — R/W R/W R/W ...
Page 95
... Transmit SLC-96 Data Link Register 2 (T1 Mode) Transmit Non-Align Frame Register (E1 Mode) Transmit SLC-96 Data Link Register 3 (T1 Mode) Transmit Si Bits of the Align Frame Register (E1 Mode) Transmit Si Bits of the Non-Align Frame Register (E1 Mode Only 276 DS26528 Octal T1/E1/J1 Transceiver R/W R/W R/W R/W R/W ...
Page 96
... Transmit Blank Channel Select Register 4 (E1 Mode Only) Transmit Channel Blocking Register 1 Transmit Channel Blocking Register 2 Transmit Channel Blocking Register 3 Transmit Channel Blocking Register 4 (E1 Mode Only) Transmit Hardware-Signaling Channel Select Register 276 DS26528 Octal T1/E1/J1 Transceiver R/W R/W R/W R/W R/W R/W R/W — ...
Page 97
... Per-Channel Loopback Enable Register 4 (E1 Mode Only) Transmit BERT Port Channel Select Register 1 Transmit BERT Port Channel Select Register 2 Transmit BERT Port Channel Select Register 3 Transmit BERT Port Channel Select Register 4 (E1 Mode Only) Reserved 97 of 276 DS26528 Octal T1/E1/J1 Transceiver R/W R/W R/W R/W R/W R/W ...
Page 98
... BERT Bit Count Register 1 BERT Bit Count Register 2 BERT Bit Count Register 3 BERT Bit Count Register 4 BERT Error Count Register 1 BERT Error Count Register 2 BERT Error Count Register 3 BERT Latched Status Register BERT Status Interrupt Mask Register 98 of 276 DS26528 Octal T1/E1/J1 Transceiver ...
Page 99
... FIS6 FIS5 BIS7 BIS6 BIS5 LIS7 LIS6 LIS5 FIM7 FIM6 FIM5 BIM7 BIM6 BIM5 LIM7 LIM6 LIM5 99 of 276 DS26528 Octal T1/E1/J1 Transceiver BIT 3 BIT 2 BIT 1 — BWE GCLE RFLOSSFS RFMSS TCBCS — LOSS TSSYNCIOSEL BFREQSEL FREQSEL MPS1 — — — ...
Page 100
... Framer Register Bit Map Table 9-7 contains the framer registers of the DS26528. Some registers have dual functionality based on the selection of T1/ operating mode in the shown below using two lines of text. The first line of text is the bit functionality for T1/J1 mode. The second line is the bit functionality in E1 mode, in italics. Bits that are not used for an operating mode are noted with a dash “ ...
Page 101
... CH15-B CH15-C CH15-D LCVC14 LCVC13 LCVC12 LCVC6 LCVC5 LCVC4 PCVC14 PCVC13 PCVC12 PCVC6 PCVC5 PCVC4 FOS14 FOS13 FOS12 FOS6 FOS5 FOS4 101 of 276 DS26528 Octal T1/E1/J1 Transceiver BIT 3 BIT 2 BIT 1 — — — CH4 CH3 CH2 CH12 CH11 CH10 CH20 ...
Page 102
... FASRC LSPC LDNC LUPC — V52LNKC RDMAC RESEM RSLIP — — ROVR RHOBT — RRAI-CI RAIS-CI — — — 102 of 276 DS26528 Octal T1/E1/J1 Transceiver BIT 3 BIT 2 BIT 1 EB11 EB10 EB9 EB3 EB2 EB1 FR3 FR2 FR1 RFDL3 RFDL2 RFDL1 CSC0 ...
Page 103
... CH6 CH5 CH15 CH14 CH13 CH23 CH22 CH21 — — — CH31 CH30 CH29 CH7 CH6 CH5 103 of 276 DS26528 Octal T1/E1/J1 Transceiver BIT 3 BIT 2 BIT 1 — — — CH4 CH3 CH2 CH12 CH11 CH10 CH20 CH19 CH18 — — — ...
Page 104
... 104 of 276 DS26528 Octal T1/E1/J1 Transceiver BIT 3 BIT 2 BIT 1 CH12 CH11 CH10 CH200 CH19 CH18 — — — CH28 CH27 CH26 CH4 CH3 CH2 CH12 CH11 CH10 CH20 CH19 CH18 — — — CH28 CH27 CH26 CH4 CH3 CH2 CH12 CH11 ...
Page 105
... CH9-D CH11-B CH11-C CH11-D CH10-B CH10-C CH10-D CH12-B CH12-C CH12-D CH11-B CH11-C CH11-D — — — CH12-B CH12-C CH12-D — — — CH13-B CH13-C CH13-D 105 of 276 DS26528 Octal T1/E1/J1 Transceiver BIT 3 BIT 2 BIT — — — — — — — ...
Page 106
... TSYNCINV TSSYNCINV TGCLKEN —— TSZS — — — — — — — — — IBS1 IBS0 IBOSEL 106 of 276 DS26528 Octal T1/E1/J1 Transceiver BIT 3 BIT 2 BIT 1 — — — CH29-A CH29-B CH29-C — — — CH30-A CH30-B CH30-C CH4 CH3 ...
Page 107
... CH31 CH30 CH29 CH7 CH6 CH5 CH15 CH14 CH13 CH23 CH22 CH21 — — — 107 of 276 DS26528 Octal T1/E1/J1 Transceiver BIT 3 BIT 2 BIT 1 TCM3 TCM2 TCM1 — TBPDIR TBPFUS BPBSE4 BPBSE3 BPBSE2 — TSEN SYNCE CRC4 TSEN SYNCE ...
Page 108
... BBC29 BBC28 EC6 EC5 EC4 EC14 EC13 EC12 EC22 EC21 EC20 BBED BBCO BECO BBED BBCO BECO 108 of 276 DS26528 Octal T1/E1/J1 Transceiver BIT 3 BIT 2 BIT 1 CH28 CH27 CH26 CH4 CH3 CH2 CH12 CH11 CH10 CH20 CH19 CH18 — — — ...
Page 109
... Global Framer Interrupt Status Register Global BERT Interrupt Status Register Global LIU Interrupt Status Register Global Framers Interrupt Mask Register Global BERT Interrupt Mask Register Global LIU Interrupt Mask Register Reserved 109 of 276 DS26528 Octal T1/E1/J1 Transceiver R/W R/W R/W R/W R/W — R/W R/W — ...
Page 110
... Bit 0: Global Interrupt Pin Inhibit (GIPI Normal operation. Interrupt pin (INTB) will toggle low on an unmasked interrupt condition Interrupt inhibit. Interrupt pin (INTB) is forced high (inactive) when this bit is set RLOFLTS GIBO — 110 of 276 DS26528 Octal T1/E1/J1 Transceiver BWE GCLE GIPI ...
Page 111
... Bit 0: Receive Channel Block/Clock Select (RCBCS). This bit controls the function of all eight RCHBLK/CLK pins RCHBLK/CLK pin outputs RCHBLK[1:8] (receive channel block RCHBLK/CLK pin outputs RCHCLK[1:8] (receive channel clock BPCLK1 BPCLK0 RFLOSSFS 0 0 IBO MODE BPCLK FREQUENCY 2.048MHz 4.096MHz 8.192MHz 16.384MHz 111 of 276 DS26528 Octal T1/E1/J1 Transceiver RFMSS TCBCS RCBCS 0 ...
Page 112
... BPCLK. This “frame pulse” can be used in conjunction with the backplane clock to provide IBO signals for a system backplane. If this bit is reset, TSSYNCIO is an input. An 8kHz frame pulse is required for transmit synchronization and IBO operation — — — 112 of 276 DS26528 Octal T1/E1/J1 Transceiver 2 1 LOSS TSSYNCIOSEL — ...
Page 113
... The external master clock is 1.544MHz or multiple thereof. Bits 1 and 0: Master Period Select 1 and 0 (MPS[1:0]). In conjunction with the FREQSEL bit, these bits select the external MCLK frequency of the signal input at the MCLK pin of the DS26528. This is shown in Table 9-11. Backplane Reference Clock Select ...
Page 114
... Table 9-12. Master Clock Input Selection FREQSEL MPS1 MPS0 MCLK (MHz ±50ppm) 2.048 4.096 8.192 16.384 1.544 3.088 6.176 12.352 114 of 276 DS26528 Octal T1/E1/J1 Transceiver ...
Page 115
... Bit 0: Channel 1 LIU Software Reset (LSRST1). LIU logic and registers are reset with a 0-to-1 transition in this bit. The reset is released when a zero is written to this bit Normal operation 1 = Reset LIU LSRST6 LSRST5 LSRST4 115 of 276 DS26528 Octal T1/E1/J1 Transceiver LSRST3 LSRST2 LSRST1 ...
Page 116
... Bit 0: Channel 1 Framer and BERT Software Reset (FSRST1). Framer logic and registers are reset with a 0-to-1 transition in this bit. The reset is released when a zero is written to this bit Normal operation 1 = Reset framer and BERT FSRST6 FSRST5 FSRST4 116 of 276 DS26528 Octal T1/E1/J1 Transceiver FSRST3 FSRST2 FSRST1 ...
Page 117
... Device Identification Register Register Address: 0F8h Bit # 7 6 Name ID7 ID6 Default 0 1 Bits Device ID (ID[7:3]). The upper five bits of the IDR are used to display the DS26528 ID. Table 9-13. Device ID Codes in this Product Family DEVICE ID7 DS26528 0 DS26524 0 DS26522 0 DS26521 0 Bits Silicon Revision Bits (ID[2:0]). The lower three bits of the IDR are used to display a sequential number denoting the die revision of the chip. The initial silicon revision = “ ...
Page 118
... Framer 3 has issued an interrupt. Bit 0: Framer Interrupt Status 2 (FIS2 Framer 2 has not issued an interrupt Framer 2 has issued an interrupt. Bit 0: Framer Interrupt Status 1 (FIS1 Framer 1 has not issued an interrupt Framer 1 has issued an interrupt FIS6 FIS5 FIS4 118 of 276 DS26528 Octal T1/E1/J1 Transceiver FIS3 FIS2 FIS1 ...
Page 119
... BERT 3 has issued an interrupt. Bit 1: BERT Interrupt Status 2 (BIS2 BERT 2 has not issued an interrupt BERT 2 has issued an interrupt. Bit 0: BERT Interrupt Status 1 (BIS1 BERT 1 has not issued an interrupt BERT 1 has issued an interrupt BIS6 BIS5 BIS4 119 of 276 DS26528 Octal T1/E1/J1 Transceiver BIS3 BIS2 BIS1 ...
Page 120
... LIU 3 has issued an interrupt. Bit 1: LIU Interrupt Status 2 (LIS2 LIU 2 has not issued an interrupt LIU 2 has issued an interrupt. Bit 0: LIU Interrupt Status 1 (LIS1 LIU 1 has not issued an interrupt LIU 1 has issued an interrupt LIS6 LIS5 LIS4 120 of 276 DS26528 Octal T1/E1/J1 Transceiver LIS3 LIS2 LIS1 ...
Page 121
... Interrupt enabled. Bit 2: Framer 3 Interrupt Mask (FIM3 Interrupt masked Interrupt enabled. Bit 1: Framer 2 Interrupt Mask (FIM2 Interrupt masked Interrupt enabled. Bit 0: Framer 1 Interrupt Mask (FIM1 Interrupt masked Interrupt enabled FIM6 FIM5 FIM4 121 of 276 DS26528 Octal T1/E1/J1 Transceiver FIM3 FIM2 FIM1 ...
Page 122
... Interrupt enabled. Bit 2: BERT Interrupt Mask 3 (BIM3 Interrupt masked Interrupt enabled. Bit 1: BERT Interrupt Mask 2 (BIM2 Interrupt masked Interrupt enabled. Bit 0: BERT Interrupt Mask 1 (BIM1 Interrupt masked Interrupt enabled BIM6 BIM5 BIM4 122 of 276 DS26528 Octal T1/E1/J1 Transceiver BIM3 BIM2 BIM1 ...
Page 123
... Interrupt enabled. Bit 2: LIU Interrupt Mask 3 (LIM3 Interrupt masked Interrupt enabled. Bit 1: LIU Interrupt Mask 2 (LIM2 Interrupt masked Interrupt enabled. Bit 0: LIU Interrupt Mask 1 (LIM1 Interrupt masked Interrupt enabled LIM6 LIM5 LIM4 123 of 276 DS26528 Octal T1/E1/J1 Transceiver LIM3 LIM2 LIM1 ...
Page 124
... Bit 6: Receive HDLC Reset (RHR). Will reset the receive HDLC controller and flush the receive FIFO. Note that this bit is a acknowledged reset. The host should set this bit and the DS26528 will clear it once the reset operation is complete. The DS26528 will complete the HDLC reset within two frames. ...
Page 125
... Bit 1: Receive Channel Bit 2 Suppress (BSE2). Set to one to stop this bit from being used. Bit 0: Receive Channel Bit 1 Suppress (BSE1). LSB of the channel. Set to one to stop this bit from being used BSE6 BSE5 BSE4 125 of 276 DS26528 Octal T1/E1/J1 Transceiver BSE3 BSE2 BSE1 ...
Page 126
... Bit 4 (E1 Mode): CAS Mode Select (CASMS The DS26528 will initiate a resync when two consecutive multiframe alignment signals have been received with an error The DS26528 will initiate a resync when two consecutive multiframe alignment signals have been received with an error multiframe has been received with all the bits in time slot 16 in state 0 ...
Page 127
... Bit 1: Receive RAI Integration Enable (RAIIE). The ESF RAI indication can be interrupted for a period not to exceed 100ms per interruption (T1.403). In ESF mode, setting RAIIE will cause the RAI status from the DS26528 to be integrated for 200ms RAI detects when 16 consecutive patterns of 00FF appear in the FDL. ...
Page 128
... Bit 0: Sa8 Change Detect Interrupt Mask (RSa8IM). This bit will enable the change detect interrupt for the Sa8 bits. Any change of state of the Sa8 bit will then generate an interrupt in RLS7.0 to indicate the change of state interrupt masked 1 = interrupt enabled — RSa4IM RSa5IM 128 of 276 DS26528 Octal T1/E1/J1 Transceiver RSa6IM RSa7IM RSa8IM ...
Page 129
... Bit 7: Receive BOC Reset (RBR). The host should set this bit to force a reset of the BOC circuitry. Note that this is an acknowledged reset, that is, the host need only set the bit and the DS26528 will clear it once the reset operation is complete (less than 250μs). Modifications to the RBF[1:0] and RBD[1:0] bits will not be applied to the BOC controller until a BOC reset has been completed ...
Page 130
... CH4 CH14 CH13 CH12 CH22 CH21 CH20 CH6 CH5 CH4 CH14 CH13 CH12 CH22 CH21 CH20 130 of 276 DS26528 Octal T1/E1/J1 Transceiver (LSB) CH3 CH2 CH1 T1RSAOI1 CH11 CH10 CH9 T1RSAOI2 CH19 CH18 CH17 T1RSAOI3 (LSB) CH3 CH2 CH1 T1RDMWE1 CH11 ...
Page 131
... CH25-A CH25-B CH11-D CH26-A CH26-B CH12-D CH27-A CH27-B CH13-D CH28-A CH28-B CH14-D CH29-A CH29-B CH15-D CH30-A CH30-B 131 of 276 DS26528 Octal T1/E1/J1 Transceiver (LSB) CH13-C CH13-D RS1 CH14-C CH14-D RS2 CH15-C CH15-D RS3 CH16-C CH16-D RS4 CH17-C CH17-D RS5 CH18-C CH18-D ...
Page 132
... Bits Path Code Violation Counter Bits (PCVC[7:0]). PCVC0 is the LSB of the 16-bit path code violation count LCVC13 LCVC12 LCVC11 LCVC5 LCVC4 LCVC3 PCVC13 PCVC12 PCVC11 PCVC5 PCVC4 PCVC3 132 of 276 DS26528 Octal T1/E1/J1 Transceiver LCVC10 LCVC9 LCVC8 LCVC2 LCVC1 LCVC0 PCVC10 PCVC9 PCVC8 PCVC2 PCVC1 PCVC0 ...
Page 133
... Bits E-Bit Counter Bits (EB[7:0]). EB0 is the LSB of the 16-bit E-bit count FOS13 FOS12 FOS11 FOS5 FOS4 FOS3 EB13 EB12 EB11 EB5 EB4 EB3 133 of 276 DS26528 Octal T1/E1/J1 Transceiver FOS10 FOS9 FOS8 FOS2 FOS1 FOS0 EB10 EB9 EB8 EB2 EB1 EB0 ...
Page 134
... Register Address: 061h + (200h x n): where for Ports Bit # 7 6 Name FR7 FR6 Default 0 0 Bits Firmware Revision (FR[7:0]). This read-only register reports the current revision of the receive firmware FR5 FR4 FR3 134 of 276 DS26528 Octal T1/E1/J1 Transceiver FR2 FR1 FR0 ...
Page 135
... Bit 1: CAS MF Sync Active (CASSA). Set while the synchronizer is searching for the CAS MF alignment word. Bit 0: FAS Sync Active (FASSA). Set while the synchronizer is searching for alignment at the FAS level RFDL5 RFDL4 RFDL3 CSC3 CSC2 CSC0 135 of 276 DS26528 Octal T1/E1/J1 Transceiver RFDL2 RFDL1 RFDL0 CRC4SA CASSA FASSA ...
Page 136
... The T1RBOC register always contains the last valid BOC received. The Receive FDL register (T1RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs bits. The LSB is received first framing mode, RFDL updates on multiframe boundaries and reports the six Fs bits in RFDL[5:0 RBOC5 RBOC4 RBOC3 136 of 276 DS26528 Octal T1/E1/J1 Transceiver RBOC2 RBOC1 RBOC0 ...
Page 137
... Bit 5: Frame Alignment Signal Bit (0). Bit 4: Frame Alignment Signal Bit (1). Bit 3: Frame Alignment Signal Bit (1). Bit 2: Frame Alignment Signal Bit (0). Bit 1: Frame Alignment Signal Bit (1). Bit 0: Frame Alignment Signal Bit (1 S=0 S=1 S 137 of 276 DS26528 Octal T1/E1/J1 Transceiver (LSB T1RSLC1 C11 C10 C9 T1RSLC2 T1RSLC3 ...
Page 138
... Bit 4: Si Bit of Frame 8 (SiF8). Bit 3: Si Bit of Frame 6 (SiF6). Bit 2: Si Bit of Frame 4 (SiF4). Bit 1: Si Bit of Frame 2 (SiF2). Bit 0: Si Bit of Frame 0 (SiF0 Sa4 Sa5 SiF10 SiF8 SiF6 138 of 276 DS26528 Octal T1/E1/J1 Transceiver Sa6 Sa7 Sa8 SiF4 SiF2 SiF0 ...
Page 139
... Bit 3: Remote Alarm Bit of Frame 7 (RRAF7). Bit 2: Remote Alarm Bit of Frame 5 (RRAF5). Bit 1: Remote Alarm Bit of Frame 3 (RRAF3). Bit 0: Remote Alarm Bit of Frame 1 (RRAF1 SiF11 SiF9 SiF7 RRAF11 RRAF9 RRAF7 139 of 276 DS26528 Octal T1/E1/J1 Transceiver SiF5 SiF3 SiF1 RRAF5 RRAF3 RRAF1 ...
Page 140
... Bit 4: Sa5 Bit of Frame 9 (RSa5F9). Bit 3: Sa5 Bit of Frame 7 (RSa5F7). Bit 2: Sa5 Bit of Frame 5 (RSa5F5). Bit 1: Sa5 Bit of Frame 3 (RSa5F3). Bit 0: Sa5 Bit of Frame 1 (RSa5F1 RSa4F11 RSa4F9 RSa4F7 RSa5F11 RSa5F9 RSa5F7 140 of 276 DS26528 Octal T1/E1/J1 Transceiver RSa4F5 RSa4F3 RSa4F1 RSa5F5 RSa5F3 RSa5F1 ...
Page 141
... Bit 4: Sa7 Bit of Frame 9 (RSa7F9). Bit 3: Sa7 Bit of Frame 7 (RSa7F7). Bit 2: Sa7 Bit of Frame 5 (RSa7F5). Bit 1: Sa7 Bit of Frame 3 (RSa7F3). Bit 0: Sa7 Bit of Frame 1 (RSa7F1 RSa6F11 RSa6F9 RSa6F7 RSa7F11 RSa7F9 RSa7F7 141 of 276 DS26528 Octal T1/E1/J1 Transceiver RSa6F5 RSa6F3 RSa6F1 RSa7F5 RSa7F3 RSa7F1 ...
Page 142
... Bit 3: Last Received Sa5 Bit (Sa5). Bit 2: Last Received Sa6 Bit (Sa6). Bit 1: Last Received Sa7 Bit (Sa7). Bit 0: Last Received Sa8 Bit (Sa8 RSa8F11 RSa8F9 RSa8F7 — Sa4 Sa5 142 of 276 DS26528 Octal T1/E1/J1 Transceiver RSa8F5 RSa8F3 RSa8F1 Sa6 Sa7 Sa8 RLS7 register to ...
Page 143
... The host is required to write or clear all device registers prior to setting this bit. Once INIT_DONE is set, the DS26528 will check the FRM_EN bit and, if enabled, will begin operation based on the initial configuration. Bit 1: Soft Reset (SFTRST). Level sensitive soft reset. Should be taken high then low to reset the receiver. ...
Page 144
... Bit 1: Sync Enable (SYNCE auto resync enabled 1 = auto resync disabled Bit 0: Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the receive-side framer is initiated. Must be cleared and set again for a subsequent resync RFM ARC SYNCC 144 of 276 DS26528 Octal T1/E1/J1 Transceiver RJC SYNCE RESYNC ...
Page 145
... Bit 0: Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the receive-side framer is initiated. Must be cleared and set again for a subsequent resync RSIGM RG802 RCRC4 RCR1 Figure 10-23 for details. 145 of 276 DS26528 Octal T1/E1/J1 Transceiver FRC SYNCE RESYNC ...
Page 146
... Bits Receive Down Code Length Definition Bits (RDN[2:0]). RDN2 RDN1 RDN0 RUP2 RUP1 RUP0 LENGTH SELECTED 1 bits 2 bits 3 bits 4 bits 5 bits 6 bits 7 bits bits LENGTH SELECTED 1 bits 2 bits 3 bits 4 bits 5 bits 6 bits 7 bits bits 146 of 276 DS26528 Octal T1/E1/J1 Transceiver RDN2 RDN1 RDN0 ...
Page 147
... Sa4 bit position. Bit 0: Receive Loss of Signal Alternate Criteria (RLOSA). Defines the criteria for a loss-of-signal condition LOS declared upon 255 consecutive zeros (125μ LOS declared upon 2048 consecutive zeros (1ms RSa6S RSa5S RSa4S 147 of 276 DS26528 Octal T1/E1/J1 Transceiver — — RLOSA ...
Page 148
... The TLCLK signal will become synchronous with RCLK instead of TCLK PLB situation, the DS26528 loops the 192 bits (248 for E1) of payload data (with BPVs corrected) from the receive section back to the transmit section. The transmitter follows the frame alignment provided by the receiver. ...
Page 149
... Bit 0: RSYNC Mode Select 1 (RSMS1). Selects frame or multiframe pulse when RSYNC pin is in output mode. In input mode (elastic store must be enabled) multiframe mode is only useful when receive-signaling reinsertion is enabled frame mode 1 = multiframe mode RSMS H100EN RSCLKM — H100EN RSCLKM 8.8.3 for more information. 149 of 276 DS26528 Octal T1/E1/J1 Transceiver RSIO RSMS2 RSMS1 RSIO RSMS2 RSMS1 ...
Page 150
... Bit 1: Receive Elastic Store Minimum Delay Mode (RESMDM elastic stores operate at full two-frame depth 1 = elastic stores operate at 32-bit depth Bit 0: Receive Elastic Store Enable (RESE elastic store is bypassed 1 = elastic store is enabled — RSZS RESALGN 150 of 276 DS26528 Octal T1/E1/J1 Transceiver RESR RESE RESMDM ...
Page 151
... Bit 6: Manual Counter Update Select (MCUS). When manual update mode is enabled with EAMS, this bit can be used to allow the incoming LATCH_CNT signal to latch all counters. Used for synchronously latching counters or multiple DS26528 cores located on the same die MECU is used to manually latch counters 1 = counters are latched on the rising edge of the LATCH_CNT signal Bit 5: Manual Error Counter Update (MECU) ...
Page 152
... Register Address: 087h + (200h x n): where for Ports Bit # 7 6 Name — — Default 0 0 Bits 1 and 0: Receive FIFO High Watermark Select (RFHWM[1:0]). RFHWM1 RFHWM0 — — RECEIVE FIFO WATERMARK (BYTES 152 of 276 DS26528 Octal T1/E1/J1 Transceiver — — RFHWM1 RFHWM0 0 ...
Page 153
... DA2 DA1 DA0 DEVICE POSITION 1st device on bus 2nd device on bus 3rd device on bus 4th device on bus 5th device on bus 6th device on bus 7th device on bus 8th device on bus IBS0 IBOSEL IBOEN 153 of 276 DS26528 Octal T1/E1/J1 Transceiver DA2 DA1 DA0 ...
Page 154
... Bit 0: Receive BERT Port Enable (RBPEN Receive BERT port is not active Receive BERT port is active — — — LENGTH SELECTED (BITS 8: — — — — — — 154 of 276 DS26528 Octal T1/E1/J1 Transceiver RSC2 RSC1 RSC0 RBPDIR RBPFUS RBPEN RBPDIR — RBPEN ...
Page 155
... Bit 1: Receive Channel Bit 2 Suppress (BPBSE2). Set to one to stop this bit from being used. Bit 0: Receive Channel Bit 1 Suppress (BPBSE1). LSB of the channel. Set to one to stop this bit from being used BPBSE6 BPBSE5 BPBSE4 155 of 276 DS26528 Octal T1/E1/J1 Transceiver BPBSE3 BPBSE2 BPBSE1 ...
Page 156
... Bit 1: Receive Loss of Signal Condition Detect (RLOSD). Rising edge detect of RLOS. Set when 192 consecutive zeros have been detected at RTIP and RRING. Bit 0: Receive Loss of Frame Condition Detect (RLOFD). Rising edge detect of RLOF. Set when the DS26528 has lost synchronized to the received data stream. ...
Page 157
... B8ZS mode is selected or not. Useful for automatically setting the line coding. Bit 0: Frame Bit Error Event (FBE). Set when a Ft (D4) or FPS (ESF) framing bit is received in error COFA 8ZD 16ZD RLS2 157 of 276 DS26528 Octal T1/E1/J1 Transceiver 2 1 SEFE B8ZS FBE 0 0 for E1 mode ...
Page 158
... CRC-4 is disabled. Bit 0: Receive Align Frame Event (RAF). Set approximately every 250μs to alert the host that Si and Sa bits are available in the RAF and RNAF registers CASRC FASRC RSA1 158 of 276 DS26528 Octal T1/E1/J1 Transceiver RSA0 RCMF RAF RLS2 for T1 mode. ...
Page 159
... Bit 0: Loop-Up Code Detected Condition Detect (LUPD). Rising edge detect of LUP. Set when the loop-up code as defined in the T1RUPCD1:T1RUPCD2 LDNC LUPC LORCD RLS3 for E1 mode. registers is being received. register is being received. register is being received. 159 of 276 DS26528 Octal T1/E1/J1 Transceiver LSPD LDND LUPD ...
Page 160
... Bit 0: Receive Distant MF Alarm Detect (RDMAD). Change of state indication. Set when bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode. This is the rising edge detect of RDMA V52LNKC RDMAC LORCD RLS3 for T1 mode. 160 of 276 DS26528 Octal T1/E1/J1 Transceiver — V52LNKD RDMAD ...
Page 161
... T1 Mode: Set every 1.5ms boundaries or every 3ms on ESF MF boundaries. E1 Mode: Set every 2.0ms on receive CAS multiframe boundaries to alert host the signaling data is available. Continues to set on an arbitrary 2.0ms boundary when CAS signaling is not enabled RSLIP — RSCOS 161 of 276 DS26528 Octal T1/E1/J1 Transceiver 1SEC TIMER RMF ...
Page 162
... Bit 0: Receive FIFO Not Empty Set Event (RNES). Set when the receive FIFO has transitioned from empty to not empty (at least one byte has been put into the FIFO). Rising edge detect of RNE ROVR RHOBT RPE 162 of 276 DS26528 Octal T1/E1/J1 Transceiver RPS RHWMS RNES ...
Page 163
... SaX bits are selected by the E1RSAIMR RRAI-CI RAIS-CI RSLC96 RLS7 for E1 mode. 8.9.5.4 for more information — — — RLS7 for T1 mode. register. 163 of 276 DS26528 Octal T1/E1/J1 Transceiver 2 1 RFDLF 8.9.4.5 for more information. T1RFDL register is full. Useful for SLC- — Sa6CD SaXCD ...
Page 164
... CH6 CH5 CH4 CH14 CH13 CH12 CH22 CH21 CH20 CH30 CH29 CH28 164 of 276 DS26528 Octal T1/E1/J1 Transceiver (LSB) CH3 CH2 CH1* RSS1 CH11 CH10 CH9 RSS2 CH19 CH18 CH17* RSS3 RSS4 CH27 CH26 CH25 ...
Page 165
... Bit 2: Receive Spare Code Definition Bit 2 (C2). A Don’t Care 7-bit length is selected. Bit 1: Receive Spare Code Definition Bit 1 (C1). A Don’t Care 7-bit length is selected. Bit 0: Receive Spare Code Definition Bit 0 (C0). A Don’t Care 7-bit length is selected 165 of 276 DS26528 Octal T1/E1/J1 Transceiver ...
Page 166
... Currently, RLS2 does not create an interrupt, therefore this bit is not used in T1 mode. The Receive Interrupt Information register (RIIR) indicates which of the DS26528 status registers are generating an interrupt. When an interrupt occurs, the host can read RIIR to quickly identify which of the receive status registers is (are) causing the interrupt(s) ...
Page 167
... Bit 2: Receive-Signaling All-Zeros Event (RSA0 interrupt masked 1 = interrupt enabled Bit 1: Receive CRC-4 Multiframe Event (RCMF interrupt masked 1 = interrupt enabled Bit 0: Receive Align Frame Event (RAF interrupt masked 1 = interrupt enabled — — RSA1 167 of 276 DS26528 Octal T1/E1/J1 Transceiver RSA0 RCMF RAF ...
Page 168
... Bit 2: Spare Code Detected Condition Detect (LSPD interrupt masked 1 = interrupt enabled Bit 1: Loop-Down Code Detected Condition Detect (LDND interrupt masked 1 = interrupt enabled Bit 0: Loop-Up Code Detected Condition Detect (LUPD interrupt masked 1 = interrupt enabled LDNC LUPC LORCD 168 of 276 DS26528 Octal T1/E1/J1 Transceiver LSPD LDND LUPD ...
Page 169
... Bit 3: Loss of Receive Clock Detect (LORCD interrupt masked 1 = interrupt enabled Bit 1: V5.2 Link Detect (V52LNKD interrupt masked 1 = interrupt enabled Bit 0: Receive Distant MF Alarm Detect (RDMAD interrupt masked 1 = interrupt enabled V52LNKC RDMAC LORCD 169 of 276 DS26528 Octal T1/E1/J1 Transceiver — V52LNKD RDMAD ...
Page 170
... Bit 2: One-Second Timer (1SEC interrupt masked 1 = interrupt enabled Bit 1: Timer Event (TIMER interrupt masked 1 = interrupt enabled Bit 0: Receive Multiframe Event (RMF interrupt masked 1 = interrupt enabled RSLIP — RSCOS 170 of 276 DS26528 Octal T1/E1/J1 Transceiver 1SEC TIMER RMF ...
Page 171
... Bit 1: Receive FIFO Above High Watermark Set Event (RHWMS interrupt masked 1 = interrupt enabled Bit 0: Receive FIFO Not Empty Set Event (RNES interrupt masked 1 = interrupt enabled ROVR RHOBT RPE 171 of 276 DS26528 Octal T1/E1/J1 Transceiver RPS RHWMS RNES ...
Page 172
... Bit 0: SaX Change Detect. This bit will enable the interrupt generated when a change of state is detected in any of the unmasked SaX bit positions. The masked or unmasked SaX bits are selected by the 0 = interrupt masked 1 = interrupt enabled RRAI-CI RAIS-CI RSLC96 — — — 172 of 276 DS26528 Octal T1/E1/J1 Transceiver RFDLF — Sa6CD SaXCD E1RSAIMR register. ...
Page 173
... CH6 CH5 CH4 CH14 CH13 CH12 CH22 CH21 CH20 CH30 CH29 CH28 173 of 276 DS26528 Octal T1/E1/J1 Transceiver (LSB) CH3 CH2 CH1 RSCSE1 CH11 CH10 CH9 RSCSE2 CH19 CH18 CH17 RSCSE3 RSCSE4 CH27 CH26 CH25 ...
Page 174
... Bit 2: Receive Up Code Definition Bit 2 (C2). A Don’t Care 7-bit length is selected. Bit 1: Receive Up Code Definition Bit 1 (C1). A Don’t Care 7-bit length is selected. Bit 0: Receive Up Code Definition Bit 0 (C0). A Don’t Care 7-bit length is selected 174 of 276 DS26528 Octal T1/E1/J1 Transceiver ...
Page 175
... Bit 2: Receive Down Code Definition Bit 2 (C2). A Don’t Care 7-bit length is selected. Bit 1: Receive Down Code Definition Bit 1 (C1). A Don’t Care 7-bit length is selected. Bit 0: Receive Down Code Definition Bit 0 (C0). A Don’t Care 7-bit length is selected 175 of 276 DS26528 Octal T1/E1/J1 Transceiver ...
Page 176
... Bit 2: Receive Alarm Indication Signal Condition (RAIS). Set when an unframed all-ones code is received at RTIP and RRING. Bit 1: Receive Loss of Signal Condition (RLOS). Set when 192 consecutive zeros have been detected after the B8ZS/HDB3 decoder. Bit 0: Receive Loss of Frame Condition (RLOF). Set when the DS26528 is not synchronized to the received data stream — ...
Page 177
... Bit 0: Receive Distant MF Alarm Condition (RDMA). Set when bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode — — LORC RRTS3 for E1 mode — — LORC RRTS3 for T1 mode. 177 of 276 DS26528 Octal T1/E1/J1 Transceiver LSP LDN LUP T1RSCD1:T1RSCD2 — V52LNK RDMA ...
Page 178
... HDLC status. The MS bit returns to a value of 1 when the Rx HDLC FIFO is empty. Bits Receive FIFO Packet Bytes Available Count (RPBA[6:0]). RPBA0 is the LSB PS1 PS0 — PACKET STATUS RPBA5 RPBA4 RPBA3 178 of 276 DS26528 Octal T1/E1/J1 Transceiver — RHWM RNE RPBA2 RPBA1 RPBA0 ...
Page 179
... RHD5 RHD4 RHD3 CH6 CH5 CH4 CH14 CH13 CH12 CH22 CH21 CH20 CH30 CH29 CH28 179 of 276 DS26528 Octal T1/E1/J1 Transceiver RHD2 RHD1 CH3 CH2 CH1 CH11 CH10 CH9 CH19 CH18 CH17 CH27 CH26 CH25 ...
Page 180
... CH20 CH30 CH29 CH28 CH6 CH5 CH4 CH14 CH13 CH12 CH22 CH21 CH20 CH30 CH29 CH28 180 of 276 DS26528 Octal T1/E1/J1 Transceiver CH3 CH2 CH1 RCBR1 CH11 CH10 CH9 RCBR2 CH19 CH18 CH17 RCBR3 RCBR4* CH25 CH27 CH26 (E1 Mode (F-bit) Only ...
Page 181
... CH20 CH30 CH29 CH28 CH6 CH5 CH4 CH14 CH13 CH12 CH22 CH21 CH20 CH30 CH29 CH28 181 of 276 DS26528 Octal T1/E1/J1 Transceiver CH3 CH2 CH1 RGCCS1 CH11 CH10 CH9 RGCCS2 CH19 CH18 CH17 RGCCS3 RGCCS4* CH25 CH27 CH26 (E1 Mode (F-bit) Only ...
Page 182
... BERT port. Multiple or all channels may be selected simultaneously CH6 CH5 CH4 CH14 CH13 CH12 CH22 CH21 CH20 CH30 CH29 CH28 182 of 276 DS26528 Octal T1/E1/J1 Transceiver (LSB) CH3 CH2 CH1 RBPCS1 CH11 CH10 CH9 RBPCS2 CH19 CH18 CH17 RBPCS3 RBPCS4 CH27 CH26 CH25 ...
Page 183
... FFh flags/idle will be transmitted until a new packet is initiated by writing new data into the FIFO. This is an acknowledged reset, that is, the host need only to set the bit and the DS26528 will clear it once the reset operation is complete. Total time for the reset is less than 250μs. ...
Page 184
... Bits Transmit HDLC Channel Select (THCS[4:0]). Determines which DSO channel will carry the HDLC message if enabled. Changes to this value are acknowledged only upon a transmit HDLC controller reset (THR at THC1.5 TBSE6 TBSE5 TBSE4 THCEN THCS4 THCS3 THCEN THCS4 THCS3 184 of 276 DS26528 Octal T1/E1/J1 Transceiver TBSE3 TBSE2 TBSE1 THCS2 THCS1 THCS0 THCS2 THCS1 THCS0 T1TBOC ...
Page 185
... Bit 0: Additional Bit 8 Insertion Control Bit (Sa8 not insert data from the TSa8 register into the transmit data stream 1 = insert data from the TSa8 register into the transmit data stream Sa4 Sa5 185 of 276 DS26528 Octal T1/E1/J1 Transceiver Sa6 Sa7 Sa8 ...
Page 186
... TIDR1:TIDR24 are T1 mode. TIDR25:TIDR32 are E1 mode CH6 CH5 CH4 CH14 CH13 CH12 CH22 CH21 CH20 CH30 CH29 CH28 186 of 276 DS26528 Octal T1/E1/J1 Transceiver (LSB) CH3 CH2 CH1 CH11 CH10 CH9 CH19 CH18 CH17 CH27 CH26 CH25 SSIE1 SSIE2 SSIE3 SSIE4 ...
Page 187
... CH10-C CH10-D CH25-A CH11-C CH11-D CH26-A CH12-C CH12-D CH27-A CH13-C CH13-D CH28-A CH14-C CH14-D CH29-A CH15-C CH15-D CH30-A 187 of 276 DS26528 Octal T1/E1/J1 Transceiver (LSB) CH13-B CH13-C CH13-D CH14-B CH14-C CH14-D CH15-B CH15-C CH15-D CH16-B CH16-C CH16-D CH17-B CH17-C CH17-D CH18-B ...
Page 188
... Idle Code Array into the transmit data stream CH6 CH5 CH4 CH14 CH13 CH12 CH22 CH21 CH20 CH30 CH29 CH28 188 of 276 DS26528 Octal T1/E1/J1 Transceiver (LSB) CH3 CH2 CH1 CH11 CH10 CH9 CH19 CH18 CH17 CH27 CH26 CH25 TCICE1 ...
Page 189
... Bit 2: Transmit BOC Bit 2 (TBOC2). Bit 1: Transmit BOC Bit 1 (TBOC1). Bit 0: Transmit BOC Bit 0 (TBOC0). LSB of the transmit BOC code FR5 FR4 FR3 TFDL5 TFDL4 TFDL3 TBOC5 TBOC4 TBOC3 189 of 276 DS26528 Octal T1/E1/J1 Transceiver FR2 FR1 FR0 TFDL2 TFDL1 TFDL0 TBOC2 TBOC1 TBOC0 ...
Page 190
... Bit 4: Additional Bit 4 (Sa4). Bit 3: Additional Bit 5 (Sa5). Bit 2: Additional Bit 6 (Sa6). Bit 1: Additional Bit 7 (Sa7). Bit 0: Additional Bit 8 (Sa8 S=0 S=1 S for E1 modes Sa4 Sa5 0 0 190 of 276 DS26528 Octal T1/E1/J1 Transceiver (LSB C11 C10 Sa6 Sa7 T1TSLC1 T1TSLC2 T1TSLC3 ...
Page 191
... Bit 4: Si Bit of Frame 9 (TSiF9). Bit 3: Si Bit of Frame 7 (TSiF7). Bit 2: Si Bit of Frame 5 (TSiF5). Bit 1: Si Bit of Frame 3 (TSiF3). Bit 0: Si Bit of Frame 1 (TSiF1 TSiF10 TSiF8 TSiF6 TSiF11 TSiF9 TSiF7 191 of 276 DS26528 Octal T1/E1/J1 Transceiver TSiF4 TSiF2 TSiF0 TSiF5 TSiF3 TSiF1 ...
Page 192
... Bit 4: Sa4 Bit of Frame 9 (TSa4F9). Bit 3: Sa4 Bit of Frame 7 (TSa4F7). Bit 2: Sa4 Bit of Frame 5 (TSa4F5). Bit 1: Sa4 Bit of Frame 3 (TSa4F3). Bit 0: Sa4 Bit of Frame 1 (TSa4F1 TRAF11 TRAF9 TRAF7 TSa4F11 TSa4F9 TSa4F7 192 of 276 DS26528 Octal T1/E1/J1 Transceiver TRAF5 TRAF3 TRAF1 TSa4F5 TSa4F3 TSa4F1 ...
Page 193
... Bit 4: Sa6 Bit of Frame 9 (TSa6F9). Bit 3: Sa6 Bit of Frame 7 (TSa6F7). Bit 2: Sa6 Bit of Frame 5 (TSa6F5). Bit 1: Sa6 Bit of Frame 3 (TSa6F3). Bit 0: Sa6 Bit of Frame 1 (TSa6F1 TSa5F11 TSa5F9 TSa5F7 TSa6F11 TSa6F9 TSa6F7 193 of 276 DS26528 Octal T1/E1/J1 Transceiver TSa5F5 TSa5F3 TSa5F1 TSa6F5 TSa6F3 TSa6F1 ...
Page 194
... Bit 4: Sa8 Bit of Frame 9 (TSa8F9). Bit 3: Sa8 Bit of Frame 7 (TSa8F7). Bit 2: Sa8 Bit of Frame 5 (TSa8F5). Bit 1: Sa8 Bit of Frame 3 (TSa8F3). Bit 0: Sa8 Bit of Frame 1 (TSa8F1 TSa7F11 TSa7F9 TSa7F7 TSa8F11 TSa8F9 TSa8F7 194 of 276 DS26528 Octal T1/E1/J1 Transceiver TSa7F5 TSa7F3 TSa7F1 TSa8F5 TSa8F3 TSa8F1 ...
Page 195
... The host is required to write or clear all device registers prior to setting this bit. Once INIT_DONE is set, the DS26528 will check the FRM_EN bit and, if enabled will begin operation based on the initial configuration. Bit 1: Soft Reset (SFTRST). Level sensitive-soft reset. Should be taken high then low to reset the transceiver. ...
Page 196
... Bit 1: Transmit Alarm Indication Signal (TAIS transmit data normally 1 = transmit an unframed all-ones code at TPOS and TNEG Bit 0: Transmit Remote Alarm Indication (TRAI not transmit remote alarm 1 = transmit remote alarm TCPT TSSE GB7S 196 of 276 DS26528 Octal T1/E1/J1 Transceiver TB8ZS TAIS TRAI ...
Page 197
... Bit 0: Transmit CRC-4 Enable (TCRC4 CRC-4 disabled 1 = CRC-4 enabled TG802 TSiS TSA1 E1TAF 8.9.4 on software signaling. THSCS1:THSCS4 and E1TNAF registers (in this mode, TCR1.7 must be set to 0) 197 of 276 DS26528 Octal T1/E1/J1 Transceiver 2 1 THDB3 TAIS TCRC4 0 0 and E1TNAF registers registers 0 0 ...
Page 198
... TLS1.3 and RLS2.7 bits, respectively. When this bit is set to one, the DS26528 will force the transmitted stream to meet this requirement no matter the content of the transmitted stream. When running B8ZS, this bit should be set to zero since B8ZS-encoded data streams cannot violate the pulse density requirements ...
Page 199
... Bit 1: Sa7 Bit Select (Sa7S). Set to one to source the Sa7 bit; set to zero to not source the Sa7 bit. Bit 0: Sa8 Bit Select (Sa8S). Set to one to source the Sa8 bit; set to zero to not source the Sa8 bit ARA Sa4S Sa5S 199 of 276 DS26528 Octal T1/E1/J1 Transceiver Sa6S Sa7S Sa8S ...
Page 200
... CRC-4 generation and insertion operates in normal mode 1 = transmit CRC-4 generation operates according to G.706 Intermediate Path Recalculation method TCSS1 TCSS0 MFRS TCSS1 TCSS0 MFRS TRANSMIT CLOCK SOURCE 8.9.15 200 of 276 DS26528 Octal T1/E1/J1 Transceiver TFM IBPV TLOOP — IBPV CRC4R for details. T1TCD1 and T1TCD2 ...