DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 172

• Manufacturer Part Number: DS26528GNA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GNA4

• Part # Aliases: 90-26528-NA4

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: For E1 mode, see RIM7.
Bit 5: Receive RAI-CI (RRAI-CI).
Bit 4: Receive AIS-CI (RAIS-CI).
Bit 3: Receive SLC-96 (RSLC96).
Bit 2: Receive FDL Register Full (RFDLF).
Bit 1: BOC Clear Event (BC).
Bit 0: BOC Detect Event (BD).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: For T1 mode, see RIM7.
Bit 1: Sa6 Codeword Detect. This bit will enable the interrupt generated when a valid codeword (per ETS 300
233) is detected in the Sa6 bits.
Bit 0: SaX Change Detect. This bit will enable the interrupt generated when a change of state is detected in any of
the unmasked SaX bit positions. The masked or unmasked SaX bits are selected by the
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
—
—
7
0
7
0
RIM7 (T1 Mode)
Receive Interrupt Mask Register 7 (BOC:FDL)
0A6h + (200h x n): where n = 0 to 7, for Ports 1 to 8
RIM7 (E1 Mode)
Receive Interrupt Mask Register 7 (BOC:FDL)
A6h + (200h x n): where n = 0 to 7, for Ports 1 to 8
—
—
6
0
6
0
RRAI-CI
—
5
0
5
0
RAIS-CI
172 of 276
—
4
0
4
0
RSLC96
—
3
0
3
0
DS26528 Octal T1/E1/J1 Transceiver
RFDLF
—
2
0
2
0
E1RSAIMR
Sa6CD
BC
1
0
1
0
register.
SaXCD
BD
0
0
0
0