cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 96

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

Table 4-10. MISC_DATA Field Bit Definitions with HEADER_MOD Bit Set
4.0 Segmentation Coprocessor
4.3 Segmentation Control and Data Structures
4.3.2 Data Buffers
4.3.3 Segmentation Buffer Descriptors
Table 4-9. Segmentation Buffer Descriptor Entry Format
4-18
NOTE(S):
= AAL3/4; used when generating OAM cells.
NOTE(S):
(1)
(2)
Word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
0
Def.
Bit
(1)
(2)
1
2
3
4
This version of word 0 is used for AAL5 and AAL0 VCCs.
This version of word 0 is used for AAL3/4 VCCs.
This definition of bits 31:16, MISC_DATA field, applies when the HEADER_MOD bit is set, RPL_VCI=0, and AAL_MODE is not
31
BASIZE_H
GFC_DATA
30
UU
29
MISC_DATA
28
Data buffers contain CPCS-SDUs for segmentation and reside in host or
SAR-shared memory. The CN8236 retrieves host data buffers from any byte
aligned PCI address using the READ Multiple PCI command. SAR-shared data
buffers must be aligned on word boundaries. Buffers contain any number of bytes
of only user data, up to a maximum of 64 KB.
SBDs reside in SAR-shared memory on word-aligned addresses. The host
controls the allocation and management of SBDs. For each buffer to be
segmented, the host utilizes one buffer descriptor from its pool of free descriptors.
the SBDs.
Tables 4-9
27
Reserved
Mindspeed Technologies
26
through
25
BUFFER_PNTR
4-13
USER_PNTR
24
describe the entry formats and field definitions for
ATM ServiceSAR Plus with xBR Traffic Management
23
NEXT_PNTR
NEXT_PNTR
22
™
PTI_DATA
21
SEG_VCC_INDEX
20
LENGTH
19
28236-DSH-001-B
18
VCI_DATA
17
CN8236
Rsvd
Rsvd
16