cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 279

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

28236-DSH-001-B
11.0 PCI Bus Interface
11.1 Overview
The PCI bus interface is compliant with PCI Local Bus Specification,
Revision 2.1. With the exception of HRST* and HINT*, this interface is
completely synchronous to the PCI bus clock (HCLK). All inputs are sampled at
the rising edge of HCLK, and all outputs are driven by the CN8236 to be valid
before the next rising edge of HCLK.
PCI bus interface logic is clocked directly from the PCI bus clock, while the
remainder of the CN8236 logic runs off separate clocks. Synchronizing registers
and FIFOs are implemented in the PCI bus interface in order to transfer data
between the PCI bus clock (HCLK) and the system (SYSCLK) clock domains.
functional blocks. The PCI bus master logic (within the device) arbitrates via the
PCI bus arbiter (external to the device) for access to the PCI bus; access to the
PCI bus automatically implies access to the bus drivers, since no other master can
be concurrently communicating with the slave logic. The bus master logic
contends for the bus on a transaction-by-transaction basis.
allowing access to chip resources by host software. The CN8236 can also act as
DMA bus master on the PCI bus. As a result, the PCI bus interface implements
the full set of address, data, and control signals required to drive the bus as
master, and contains the logic required to support arbitration for the PCI bus. The
DMA coprocessor and the PCI bus interface are closely linked and, hence, are
shown as one unit.
The maximum PCI bus clock rate supported by the CN8236 is 33 MHz. The
The PCI bus drivers are shared between master and slave bus interface
The PCI bus interface responds to read and write requests by the host CPU,
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