cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 323

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
0x18
This register provides system control and configuration bits that are not directly associated with the reassembly
and segmentation coprocessors. The majority of these bits are configuration bits (which occur at initialization
time) and are not changed dynamically. The assertion of the HRST* system reset pin clears all bits in the
CONFIG1 register for backward compatibility.
28236-DSH-001-B
NOTE(S):
(1)
31–24
20–18
17–13
12–9
8–4
9–7
6–0
Bit
Bit
23
22
21
11
10
3
2
1
0
If 1 wait state is selected, PWAIT function does not work.
—
Configuration Register 1 (CONFIG1)
Field
Size
Field
Size
8
1
1
1
3
5
4
5
1
1
1
1
1
1
3
7
Reserved
MULTI_CLK
MULTI_PHY
UTOP16
NUM_PORTS[2:0]
SLAVE_ADDR[4:0]
TAG_SIZE[3:0]
PHYBANK[4:0]
Reserved
TX_FIFO_FLUSH_EN
INCFIFO_SZ
NEW_PMOAM
LP_BWAIT
MEMCTRL
BANKSIZE[2:0]
DIVIDER[6:0]
Name
Name
Mindspeed Technologies
Set to 0.
If logic high, selects separate UTOPIA transmit and receive clocks. If logic
low, both clocks use the RxClk input.
If logic high, multi-PHY operation is enabled.
If logic high, UTOPIA 16 bit interface is enabled; otherwise 8-bit interface.
Number of PHY ports to poll when in Master UTOPIA Mode starting with
address 0. Number of ports = (NUM_PORTS + 1)
When in Slave UTOPIA Multi-PHY Mode, this is the UTOPIA device address
of the SAR. When in Master Non-Multi-PHY Mode, this is the address
present on both TxAddr and RxAddr.
Select Tag size. Valid range is 0 to 11. In 16 bit mode (UTOP16 = 1), only
even size tags are valid.
Physical Chip Bank Select. This value is placed on LADDR[13:9] when a
PHY1 or PHY2 control access occurs.
Set to 0.
Enables TX_FIFO_FLUSH mechanism. This mechanism is valid only in
UTOPIA master and multi-PHY modes.
Incoming DMA FIFO buffer size. Logic high sets the FIFO buffer to 8 KB,
logic low to 2 KB.
When a logic high, the NEW_PMOAM mechanism is enabled.
Selects 0 or 1 wait states between consecutive data cycles during local
processor burst accesses. Set to logic low for standalone operation mode.
Selects 0 or 1 wait states SAR-shared memory (1- or 2-cycle).
Selects size of memory banks for contiguous memory support. See
Section
Pre-scaler for SYSCLK which advances the counter in the CLOCK register.
SYSCLK is divided by the divider value; if 0, divided by 128.
9.2, for further explanation.
™
Description
Description
14.0 CN8236 Registers
14.2 System Registers
(1)
14-7