cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 66

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

2.0 Architecture Overview
2.10 Logic Diagram and Pin Descriptions
Table 2-1. Hardware Signal Definitions (4 of 6)
2-32
UTOPIA1
PROCMODE
PADDR[1:0]
PBSEL[1:0]
PBE[3:0]*
PCS*
(PHYCS1*)
PAS*
PWNR
PWAIT*
PBLAST*
(PHYCS2*)
PRDY*
Pin Label
UTOPIA Mode Select
Processor Mode Select
Word Select Inputs
Bank Select Inputs
Write Byte-Enables
SAR Chip Select
ATM PHY Chip Select
(in standalone mode)
Address Strobe
Write/not Read
Processor Wait
Burst Last
ATM PHY Chip Select
(in standalone mode)
Memory Ready
Signal Name
Mindspeed Technologies
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
I
I
Selects level 1/level 2 operation. In level 1 mode, address pins
are forced to be outputs independent of master/slave mode.
This input has a pullup resistor so the default is UTOPIA
level 1 mode. When UTOPIA1 input is a logic high, the
UTOPIA address signals, TxAddr[4:0] and RxAddr[4:0], are
forced as outputs.
When grounded, this input selects the local processor mode.
When pulled to a logic high, the standalone mode is selected.
The PADDR[1,0] inputs are connected to the word select field
of the CPU address bus (address bits [3, 2] for the Intel
i80960CA processor, which can perform 4-word burst
transactions). These inputs are used by the CN8236 to allow
single-cycle bursts to be performed without requiring very
short memory access times.
Select one of four banks of memory to be accessed. They are
decoded by the memory controller to generate the appropriate
chip/bank selects to the external memory.
Supplies byte enables for each local processor memory
access. These pins are only relevant during writes by the local
processor to SAR-shared memory. Each byte enable line
corresponds to a specific byte lane in the LDATA[31:0] data
bus: PBE[0]* corresponds to LDATA[7:0], PBE[1]* to
LDATA[15:8], PBE[2]* to LDATA[23:16], and PBE[3]* to
LDATA[31:24].
In local processor mode with PROCMODE tied low, PCS* is
the SAR chip select input. In standalone mode, this pin is
PHYCS1*, which can be connected to the chip select input of
the Mindspeed PHY device.
Indicates a local processor address cycle. In standalone
mode, PAS* is used to drive the AS* pin of the Mindspeed
PHY device.
The PWNR input indicates the direction of a local processor
transfer. A logic 1 indicates a write; a logic 0 indicates a read.
During standalone mode, this output provides the same
function for the Mindspeed PHY device.
Used by the local processor or external logic to insert wait
states for read or write transactions.
In local processor mode, this input is used by the processor
to indicate the end of a transaction. During standalone mode,
this output is a second chip select, PHYCS2*.
Signals that the memory or control register has accepted the
data on a write, or that data is available to latch by the local
processor on a read cycle.
ATM ServiceSAR Plus with xBR Traffic Management
™
Definition
28236-DSH-001-B
CN8236