cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 350

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

14.0 CN8236 Registers
14.6 Counters and Status Registers
14.6.2 Local Processor Interrupt Status Registers
The Local Processor Interrupt Status registers contain all the interruptible status bits for the local processor. The
corresponding interrupt enables are located in the LP_IMASKx registers. Status types are defined as follows:
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Mindspeed Technologies
Level sensitive status—A logic 1 on the status bit causes an interrupt
when enabled by the corresponding IMASK bit. Reading the status
does not clear the status or interrupt. The source of the condition
causing the status must be cleared before the status or interrupt is
cleared.
Event driven status—A 0 > 1 transition on the status bit causes an
interrupt when enabled. Reading the status register clears the status bit
and the interrupt.
Dual event status—A 0 > 1 and 1 > 0 transition on the status bit can be
enabled to cause an interrupt. Reading the status register clears the
status bit and the interrupt.
NOTE:
Only local processor reads reset the status bits in the
LP_ISTAT0 register.
ATM ServiceSAR Plus with xBR Traffic Management
™
28236-DSH-001-B
CN8236