cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 61

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Figure 2-11. CN8236 Logic Diagram (2 of 3)
28236-DSH-001-B
Processor Mode Select
SAR/ATM Chip Select
Framer Control/Clock
Local Processor Wait
Framer Configuration
Framer Configuration
Transmit Cell Marker
Receive Cell Marker
Receive Data Parity
Write Byte-Enables
Receive Address
Transmit Enable
Self-Test Failed
Receive Enable
Address Strobe
Write not Read
Transmit Clock
Transmit Flag
Receive Data
Receive Flag
Word Select
Word Select
Bank Select
Bank Select
Burst Last
Control
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
AF12
AE12
AD14
AF15
AF16
AC14
AE5
AF5
AC6
AD6
AE6
AF6
AC7
AD7
AE7
AF7
AC8
AD8
AE8
AF8
AC9
AF9
AF2
AE3
AF3
AD4
AE4
AD5
AC10
AE11
AD10
AC13
AD12
B16
B10
C10
D11
A10
B12
C12
D12
C11
A15
D14
C14
A13
C13
C15
I = Input, O = Output, OD = Open Drain Output
Mindspeed Technologies
PROCMODE
PADDR1
PADDR0
PBSEL1
PBSEL0
PBE3*
PBE2*
PBE1*
PBE0*
PCS* (PHYCS1*)
PAS*
PBLAST* (PHYCS2*)
PWAIT*
PWNR
PFAIL*
FRCFG1
FRCFG0
UTOPIA1
TXSOC
TXCLAV
TXEN*
RXD15
RXD14
RXD13
RXD12
RXD11
RXD10
RXD9
RXD8
RXD7
RXD6
RXD5
RXD4
RXD3
RXD2
RXD1
RXD0
RXADDR4
RXADDR3
RXADDR2
RXADDR1
RXADDR0
RXPAR
RXSOC
RXCLAV
RXEN*
RXCLK(FRCTRL)
TXCLK
The symbol (*) Indicates Active Low
ATM Physical
Local Bus
Interface
Processor
Interface
TXADDR4
TXADDR3
TXADDR2
TXADDR1
TXADDR0
PDAEN*
TXPAR
TXD15
TXD14
TXD13
TXD12
TXD11
TXD10
PRDY*
PRST*
TXD9
TXD8
TXD7
TXD6
TXD5
TXD4
TXD3
TXD2
TXD1
TXD0
PINT*
™
2.10 Logic Diagram and Pin Descriptions
AC16
AF17
AE17
AD17
AC17
AE18
AD18
AC18
AF19
AE19
AF20
AE20
AD20
AC20
AF21
AE21
AC21
AF22
AE22
AD22
AC22
AE16
B13
B15
A16
D15
OD
I/O
O
O
O
I/O
O
2.0 Architecture Overview
Transmit Data
Transmit Address
Transmit Data Parity
Memory Ready
Data/Address Enable
Reset Output
Interrupt Output
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